Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30737	1			T2	231		T6	11		T8	2
auto[SpiFlashAddrCfg]	6601	1			T2	42		T6	1		T11	2
auto[SpiFlashAddr3b]	8282	1			T2	28		T4	4		T6	5
auto[SpiFlashAddr4b]	6560	1			T2	29		T6	3		T12	42

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29313

1

T2

245

T4

4

T6

11

auto[1]

22867

1

T2

85

T6

9

T12

197

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28179

1

T2

176

T6

13

T8

4

auto[1]

24001

1

T2

154

T4

4

T6

7

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34998	1			T2	261		T4	2		T6	12
values[1]	943	1			T2	2		T12	4		T49	2
values[2]	1300	1			T2	2		T6	3		T12	9
values[3]	1292	1			T2	3		T4	2		T12	11
values[4]	1256	1			T2	6		T12	8		T14	1
values[5]	1293	1			T2	5		T12	6		T14	4
values[6]	1216	1			T2	10		T11	2		T12	10
values[7]	1278	1			T2	4		T6	2		T12	3
values[8]	8604	1			T2	37		T6	3		T8	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27603

1

T4

4

T8

4

T9

4

auto[1]

24577

1

T2

330

T6

20

T12

339

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

50310

1

T2

320

T4

4

T6

20

write

1870

1

T2

10

T12

14

T27

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17230

1

T2

80

T6

6

T11

4

valids[0x1]

34950

1

T2

250

T4

4

T6

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1376	1			T2	7		T6	2		T12	10
internal_process_ops[0x5a]	1466	1			T2	6		T4	2		T9	2
internal_process_ops[0x05]	18507	1			T2	176		T12	111		T14	21
internal_process_ops[0x35]	1481	1			T2	4		T6	3		T9	2
internal_process_ops[0x15]	1379	1			T2	9		T6	2		T8	2
internal_process_ops[0x03]	923	1			T2	1		T6	1		T12	3
internal_process_ops[0x0b]	947	1			T2	2		T12	2		T20	2
internal_process_ops[0x3b]	907	1			T12	7		T27	1		T15	7
internal_process_ops[0x6b]	930	1			T2	1		T12	4		T15	5
internal_process_ops[0xbb]	948	1			T2	1		T6	1		T11	2
internal_process_ops[0xeb]	945	1			T11	2		T12	3		T14	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51274

1

T2

326

T4

4

T6

20

auto[1]

906

1

T2

4

T12

11

T27

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50363

1

T2

317

T4

4

T6

20

auto[1]

1817

1

T2

13

T12

9

T14

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9510

1

T8

2

T9

2

T20

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5806

1

T15

55

T31

10

T30

9

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1898

1

T11

2

T20

2

T15

37

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1588

1

T15

14

T31

5

T30

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2340

1

T4

4

T8

2

T9

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2025

1

T15

22

T31

4

T30

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1925

1

T15

41

T28

4

T29

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1587

1

T15

24

T31

7

T30

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

93

1

T32

2

T171

2

T172

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

40

1

T15

2

T32

1

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

42

1

T15

1

T34

1

T173

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

50

1

T30

1

T32

1

T34

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

61

1

T15

1

T28

2

T34

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

57

1

T30

1

T34

1

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

47

1

T32

3

T34

3

T173

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

64

1

T38

1

T152

2

T173

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T38

4

T152

3

T174

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

48

1

T30

1

T34

2

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

65

1

T38

1

T175

5

T176

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

79

1

T15

2

T30

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

66

1

T15

1

T30

1

T152

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

53

1

T34

1

T37

2

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T31

1

T96

1

T38

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

45

1

T30

1

T35

1

T36

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8287

1

T2

200

T6

6

T12

76

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6697

1

T2

29

T6

5

T12

107

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1341

1

T2

21

T6

1

T12

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1330

1

T2

18

T12

28

T14

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1665

1

T2

10

T6

3

T12

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1733

1

T2

18

T6

2

T12

33

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1370

1

T2

9

T6

1

T12

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1208

1

T2

15

T6

2

T12

23

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

43

1

T16

1

T92

1

T177

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

63

1

T2

1

T27

3

T70

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

48

1

T2

1

T16

1

T73

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T27

1

T43

1

T178

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

45

1

T16

3

T70

2

T179

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

61

1

T2

1

T12

4

T27

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

53

1

T2

2

T160

2

T180

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

56

1

T12

2

T16

1

T92

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T27

3

T92

1

T160

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

53

1

T43

2

T70

2

T85

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T16

2

T72

2

T179

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

65

1

T12

3

T27

4

T70

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T2

2

T12

2

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

55

1

T2

1

T12

2

T72

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T2

1

T12

1

T16

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

59

1

T2

1

T16

1

T72

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3636	1			T15	52		T28	4		T33	4
auto[0]	values[0]	valids[0x1]	14121	1			T4	2		T8	2		T9	4
auto[0]	values[1]	valids[0x1]	478	1			T15	12		T30	4		T32	4
auto[0]	values[2]	valids[0x0]	500	1			T15	3		T31	2		T30	2
auto[0]	values[2]	valids[0x1]	255	1			T15	1		T31	1		T32	7
auto[0]	values[3]	valids[0x0]	499	1			T15	12		T31	3		T30	1
auto[0]	values[3]	valids[0x1]	260	1			T4	2		T15	2		T32	3
auto[0]	values[4]	valids[0x0]	463	1			T15	10		T30	4		T32	13
auto[0]	values[4]	valids[0x1]	260	1			T15	6		T31	1		T32	9
auto[0]	values[5]	valids[0x0]	478	1			T15	2		T29	2		T31	3
auto[0]	values[5]	valids[0x1]	279	1			T15	6		T30	2		T32	5
auto[0]	values[6]	valids[0x0]	414	1			T11	2		T15	5		T28	2
auto[0]	values[6]	valids[0x1]	260	1			T15	3		T31	4		T30	1
auto[0]	values[7]	valids[0x0]	474	1			T15	7		T31	2		T30	3
auto[0]	values[7]	valids[0x1]	269	1			T20	2		T15	8		T30	4
auto[0]	values[8]	valids[0x0]	3134	1			T11	2		T15	38		T31	10
auto[0]	values[8]	valids[0x1]	1823	1			T8	2		T15	26		T31	9
auto[1]	values[0]	valids[0x0]	3600	1			T2	41		T6	3		T12	47
auto[1]	values[0]	valids[0x1]	13641	1			T2	220		T6	9		T12	163
auto[1]	values[1]	valids[0x1]	465	1			T2	2		T12	4		T49	2
auto[1]	values[2]	valids[0x0]	331	1			T2	1		T12	6		T14	2
auto[1]	values[2]	valids[0x1]	214	1			T2	1		T6	3		T12	3
auto[1]	values[3]	valids[0x0]	308	1			T12	8		T14	3		T27	1
auto[1]	values[3]	valids[0x1]	225	1			T2	3		T12	3		T27	10
auto[1]	values[4]	valids[0x0]	335	1			T2	2		T12	5		T14	1
auto[1]	values[4]	valids[0x1]	198	1			T2	4		T12	3		T27	2
auto[1]	values[5]	valids[0x0]	299	1			T2	4		T12	5		T14	4
auto[1]	values[5]	valids[0x1]	237	1			T2	1		T12	1		T49	2
auto[1]	values[6]	valids[0x0]	313	1			T2	8		T12	7		T14	1
auto[1]	values[6]	valids[0x1]	229	1			T2	2		T12	3		T14	1
auto[1]	values[7]	valids[0x0]	332	1			T2	4		T6	1		T12	2
auto[1]	values[7]	valids[0x1]	203	1			T6	1		T12	1		T27	4
auto[1]	values[8]	valids[0x0]	2114	1			T2	20		T6	2		T12	52
auto[1]	values[8]	valids[0x1]	1533	1			T2	17		T6	1		T12	26