Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3109194

1

T2

9454

T4

1

T6

2544

auto[1]

17084

1

T2

170

T12

99

T14

20

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927835

1

T2

62

T4

1

T6

10

auto[1]

2198443

1

T2

9562

T6

2534

T8

512

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	686403	1			T2	23		T4	1		T6	271
auto[524288:1048575]	333939	1			T2	4394		T9	125		T11	1
auto[1048576:1572863]	311201	1			T2	532		T9	1089		T12	595
auto[1572864:2097151]	361012	1			T2	828		T9	48		T12	4
auto[2097152:2621439]	355930	1			T2	2425		T6	2267		T9	902
auto[2621440:3145727]	375028	1			T2	642		T6	6		T9	119
auto[3145728:3670015]	337108	1			T2	779		T11	2		T12	1030
auto[3670016:4194303]	365657	1			T2	1		T9	1152		T12	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2218062

1

T2

9618

T4

1

T6

2544

auto[1]

908216

1

T2

6

T9

5568

T11

5047

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2741011

1

T2

8757

T4

1

T6

2544

auto[1]

385267

1

T2

867

T12

1077

T14

19

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	219240	1			T2	4		T4	1		T6	8
auto[0]	auto[0]	auto[0:524287]	auto[1]	404900	1			T2	2		T6	263		T8	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	85909	1			T2	16		T9	125		T11	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	197289	1			T2	4300		T12	3939		T49	675
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103019	1			T2	5		T9	1089		T12	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	184667	1			T2	14		T12	2		T14	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	102551	1			T9	48		T12	2		T14	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	216715	1			T2	515		T14	128		T49	2622
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	86929	1			T2	4		T6	1		T9	902
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	218061	1			T2	2414		T6	2266		T12	1794
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	95390	1			T2	2		T6	1		T9	119
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	221240	1			T2	640		T6	5		T12	1029
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	101594	1			T2	7		T11	2		T12	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	187361	1			T2	709		T12	1024		T27	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	126839	1			T2	1		T9	1152		T12	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	175662	1			T14	128		T49	128		T27	128
auto[0]	auto[1]	auto[0:524287]	auto[0]	1595	1			T27	4		T16	3		T43	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	57544	1			T27	2		T16	148		T43	1809
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	312	1			T2	4		T12	7		T16	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48468	1			T2	5		T12	513		T43	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	276	1			T2	1		T12	3		T27	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	20886	1			T2	512		T12	514		T16	258
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	407	1			T2	5		T12	2		T15	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	39608	1			T2	294		T16	257		T92	4191
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	285	1			T12	1		T15	3		T43	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48926	1			T15	1		T43	256		T32	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	448	1			T12	1		T27	4		T15	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56001	1			T27	1		T15	1		T92	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	338	1			T14	2		T27	8		T15	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46008	1			T14	1		T27	513		T16	3317
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	882	1			T16	10		T43	1		T32	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	59844	1			T27	512		T16	690		T32	2504
auto[1]	auto[0]	auto[0:524287]	auto[0]	269	1			T2	2		T27	1		T15	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2231	1			T2	15		T27	3		T15	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	162	1			T2	3		T12	1		T49	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1457	1			T2	34		T49	3		T27	8
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	183	1			T12	2		T27	1		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1662	1			T12	31		T27	12		T15	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	167	1			T49	1		T15	3		T32	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1265	1			T49	14		T15	8		T32	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	160	1			T2	1		T12	2		T14	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1192	1			T2	6		T12	13		T14	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	182	1			T12	1		T27	1		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1369	1			T12	13		T27	5		T15	31
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	151	1			T2	4		T27	1		T92	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1223	1			T2	59		T27	18		T70	12
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	191	1			T15	1		T70	2		T160	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1781	1			T15	15		T70	26		T160	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	48	1			T27	2		T16	1		T43	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	576	1			T27	42		T16	2		T70	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	37	1			T2	2		T12	1		T34	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	305	1			T2	30		T34	20		T280	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	42	1			T12	2		T16	2		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	466	1			T12	33		T16	43		T280	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	43	1			T2	1		T16	1		T73	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	256	1			T2	13		T16	5		T73	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T15	1		T32	1		T34	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	334	1			T32	3		T34	15		T73	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	53	1			T27	1		T15	1		T92	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	345	1			T27	81		T15	5		T92	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T14	1		T27	1		T85	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	389	1			T14	15		T27	16		T34	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	46	1			T16	6		T38	1		T178	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	412	1			T16	3		T38	2		T178	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1821828	1			T2	8632		T4	1		T6	2544
auto[0]	auto[0]	auto[1]	905538	1			T2	1		T9	5568		T11	5047
auto[0]	auto[1]	auto[0]	379488	1			T2	821		T12	1041		T14	2
auto[0]	auto[1]	auto[1]	2340	1			T14	1		T33	1		T70	1
auto[1]	auto[0]	auto[0]	13368	1			T2	120		T12	59		T14	4
auto[1]	auto[0]	auto[1]	277	1			T2	4		T12	4		T49	4
auto[1]	auto[1]	auto[0]	3378	1			T2	45		T12	34		T14	16
auto[1]	auto[1]	auto[1]	61	1			T2	1		T12	2		T15	1