Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16156

1

T4

4

T8

4

T9

4

auto[1]

11447

1

T15

118

T31

27

T30

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3391	1			T15	20		T28	27		T31	40
values[1]	3768	1			T20	8		T30	20		T32	40
values[2]	4326	1			T15	136		T32	20		T181	10
values[3]	3122	1			T8	4		T15	76		T33	4
values[4]	3424	1			T15	61		T30	20		T32	93
values[5]	3501	1			T9	4		T11	4		T32	41
values[6]	3200	1			T15	62		T30	30		T97	12
values[7]	2871	1			T4	4		T29	2		T30	31

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3049	1			T9	4		T15	20		T30	40
values[1]	4152	1			T15	20		T32	47		T182	24
values[2]	3536	1			T4	4		T8	4		T15	22
values[3]	3529	1			T20	8		T15	40		T30	31
values[4]	3406	1			T15	52		T47	16		T35	20
values[5]	2971	1			T15	82		T33	4		T29	2
values[6]	3501	1			T15	36		T28	27		T30	30
values[7]	3459	1			T11	4		T15	83		T32	21

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	152	1			T205	2		T211	4		T186	15
auto[0]	values[0]	values[1]	348	1			T175	30		T174	15		T203	16
auto[0]	values[0]	values[2]	219	1			T31	15		T37	10		T173	25
auto[0]	values[0]	values[3]	264	1			T34	15		T59	8		T221	22
auto[0]	values[0]	values[4]	254	1			T34	11		T39	16		T175	27
auto[0]	values[0]	values[5]	372	1			T15	10		T31	7		T32	9
auto[0]	values[0]	values[6]	215	1			T28	27		T201	31		T38	6
auto[0]	values[0]	values[7]	249	1			T152	12		T229	35		T157	6
auto[0]	values[1]	values[0]	320	1			T30	16		T32	10		T187	18
auto[0]	values[1]	values[1]	228	1			T182	24		T199	10		T152	14
auto[0]	values[1]	values[2]	241	1			T171	17		T152	9		T188	12
auto[0]	values[1]	values[3]	349	1			T20	8		T289	2		T192	38
auto[0]	values[1]	values[4]	307	1			T38	14		T207	16		T232	10
auto[0]	values[1]	values[5]	188	1			T32	6		T38	16		T277	6
auto[0]	values[1]	values[6]	386	1			T96	38		T214	12		T290	18
auto[0]	values[1]	values[7]	213	1			T60	13		T62	12		T155	14
auto[0]	values[2]	values[0]	350	1			T175	95		T173	10		T60	23
auto[0]	values[2]	values[1]	371	1			T181	10		T34	45		T37	14
auto[0]	values[2]	values[2]	280	1			T32	9		T220	8		T175	9
auto[0]	values[2]	values[3]	255	1			T37	16		T175	76		T176	9
auto[0]	values[2]	values[4]	373	1			T15	12		T47	16		T152	10
auto[0]	values[2]	values[5]	182	1			T15	18		T34	12		T186	6
auto[0]	values[2]	values[6]	243	1			T175	19		T174	30		T192	35
auto[0]	values[2]	values[7]	441	1			T15	81		T217	8		T34	26
auto[0]	values[3]	values[0]	199	1			T15	11		T34	21		T175	11
auto[0]	values[3]	values[1]	341	1			T35	15		T192	21		T291	12
auto[0]	values[3]	values[2]	117	1			T8	4		T31	11		T30	23
auto[0]	values[3]	values[3]	153	1			T276	16		T175	11		T229	10
auto[0]	values[3]	values[4]	185	1			T15	13		T152	17		T186	14
auto[0]	values[3]	values[5]	377	1			T33	4		T292	2		T293	20
auto[0]	values[3]	values[6]	239	1			T15	11		T189	2		T38	8
auto[0]	values[3]	values[7]	211	1			T38	20		T39	45		T186	9
auto[0]	values[4]	values[0]	256	1			T30	14		T32	12		T37	22
auto[0]	values[4]	values[1]	206	1			T15	12		T32	18		T37	7
auto[0]	values[4]	values[2]	331	1			T34	28		T39	15		T175	10
auto[0]	values[4]	values[3]	270	1			T15	9		T173	9		T216	24
auto[0]	values[4]	values[4]	184	1			T35	11		T243	33		T157	14
auto[0]	values[4]	values[5]	257	1			T15	19		T98	8		T39	15
auto[0]	values[4]	values[6]	165	1			T32	14		T173	24		T243	19
auto[0]	values[4]	values[7]	334	1			T32	12		T186	26		T221	26
auto[0]	values[5]	values[0]	216	1			T9	4		T38	11		T173	12
auto[0]	values[5]	values[1]	284	1			T294	10		T175	23		T212	24
auto[0]	values[5]	values[2]	296	1			T32	16		T34	10		T152	11
auto[0]	values[5]	values[3]	187	1			T96	15		T39	11		T295	8
auto[0]	values[5]	values[4]	226	1			T38	11		T39	11		T278	12
auto[0]	values[5]	values[5]	166	1			T37	11		T175	13		T186	9
auto[0]	values[5]	values[6]	437	1			T32	12		T96	29		T152	9
auto[0]	values[5]	values[7]	218	1			T11	4		T159	2		T198	2
auto[0]	values[6]	values[0]	188	1			T208	12		T296	27		T279	18
auto[0]	values[6]	values[1]	252	1			T32	9		T38	6		T156	35
auto[0]	values[6]	values[2]	223	1			T15	11		T34	15		T190	12
auto[0]	values[6]	values[3]	270	1			T15	15		T152	11		T175	14
auto[0]	values[6]	values[4]	170	1			T37	11		T152	22		T236	10
auto[0]	values[6]	values[5]	197	1			T15	15		T97	12		T23	12
auto[0]	values[6]	values[6]	275	1			T30	25		T32	12		T34	10
auto[0]	values[6]	values[7]	235	1			T96	11		T200	2		T38	10
auto[0]	values[7]	values[0]	84	1			T176	6		T226	4		T157	19
auto[0]	values[7]	values[1]	218	1			T39	12		T152	24		T173	9
auto[0]	values[7]	values[2]	355	1			T4	4		T87	6		T174	7
auto[0]	values[7]	values[3]	224	1			T30	27		T39	12		T174	15
auto[0]	values[7]	values[4]	317	1			T188	9		T203	17		T154	8
auto[0]	values[7]	values[5]	163	1			T29	2		T34	12		T38	24
auto[0]	values[7]	values[6]	142	1			T93	20		T37	12		T297	2
auto[0]	values[7]	values[7]	188	1			T175	11		T174	15		T298	23
auto[1]	values[0]	values[0]	108	1			T186	5		T193	12		T158	4
auto[1]	values[0]	values[1]	338	1			T175	5		T174	5		T203	7
auto[1]	values[0]	values[2]	80	1			T31	5		T37	29		T173	7
auto[1]	values[0]	values[3]	180	1			T34	5		T221	18		T207	8
auto[1]	values[0]	values[4]	200	1			T34	9		T39	4		T175	18
auto[1]	values[0]	values[5]	137	1			T15	10		T31	13		T32	11
auto[1]	values[0]	values[6]	118	1			T38	14		T203	8		T60	10
auto[1]	values[0]	values[7]	157	1			T152	9		T229	11		T157	25
auto[1]	values[1]	values[0]	183	1			T30	4		T32	10		T173	31
auto[1]	values[1]	values[1]	300	1			T152	6		T175	12		T188	8
auto[1]	values[1]	values[2]	122	1			T171	9		T152	11		T188	8
auto[1]	values[1]	values[3]	174	1			T192	7		T224	2		T207	12
auto[1]	values[1]	values[4]	169	1			T38	12		T207	12		T232	10
auto[1]	values[1]	values[5]	148	1			T32	14		T38	10		T176	6
auto[1]	values[1]	values[6]	155	1			T96	13		T225	2		T175	13
auto[1]	values[1]	values[7]	285	1			T60	21		T155	9		T158	5
auto[1]	values[2]	values[0]	239	1			T175	8		T173	10		T60	18
auto[1]	values[2]	values[1]	217	1			T34	38		T37	6		T175	13
auto[1]	values[2]	values[2]	201	1			T32	11		T175	11		T174	8
auto[1]	values[2]	values[3]	302	1			T37	4		T175	4		T176	25
auto[1]	values[2]	values[4]	319	1			T15	20		T152	10		T173	21
auto[1]	values[2]	values[5]	115	1			T15	3		T34	16		T186	14
auto[1]	values[2]	values[6]	240	1			T175	9		T174	11		T192	5
auto[1]	values[2]	values[7]	198	1			T15	2		T34	47		T153	8
auto[1]	values[3]	values[0]	120	1			T15	9		T34	3		T175	9
auto[1]	values[3]	values[1]	204	1			T273	12		T35	8		T192	4
auto[1]	values[3]	values[2]	99	1			T31	9		T30	11		T60	6
auto[1]	values[3]	values[3]	125	1			T175	13		T229	10		T206	5
auto[1]	values[3]	values[4]	170	1			T15	7		T152	7		T186	10
auto[1]	values[3]	values[5]	69	1			T131	11		T260	7		T237	16
auto[1]	values[3]	values[6]	276	1			T15	25		T38	12		T186	8
auto[1]	values[3]	values[7]	237	1			T38	8		T39	13		T186	14
auto[1]	values[4]	values[0]	163	1			T30	6		T32	8		T37	18
auto[1]	values[4]	values[1]	278	1			T15	8		T32	9		T222	10
auto[1]	values[4]	values[2]	223	1			T34	9		T36	4		T39	5
auto[1]	values[4]	values[3]	246	1			T15	11		T173	59		T206	10
auto[1]	values[4]	values[4]	139	1			T35	9		T243	10		T157	9
auto[1]	values[4]	values[5]	142	1			T15	2		T39	8		T174	7
auto[1]	values[4]	values[6]	91	1			T32	11		T173	9		T243	10
auto[1]	values[4]	values[7]	139	1			T32	9		T186	8		T221	25
auto[1]	values[5]	values[0]	130	1			T38	14		T173	8		T176	7
auto[1]	values[5]	values[1]	151	1			T299	14		T175	20		T173	38
auto[1]	values[5]	values[2]	317	1			T32	4		T34	53		T152	10
auto[1]	values[5]	values[3]	272	1			T96	5		T39	36		T243	12
auto[1]	values[5]	values[4]	141	1			T38	9		T39	9		T60	7
auto[1]	values[5]	values[5]	128	1			T37	9		T175	28		T186	11
auto[1]	values[5]	values[6]	274	1			T32	9		T96	10		T152	15
auto[1]	values[5]	values[7]	58	1			T251	12		T242	21		T133	3
auto[1]	values[6]	values[0]	169	1			T193	6		T243	22		T133	37
auto[1]	values[6]	values[1]	246	1			T32	11		T38	14		T40	8
auto[1]	values[6]	values[2]	262	1			T15	11		T34	11		T38	8
auto[1]	values[6]	values[3]	135	1			T15	5		T152	11		T175	6
auto[1]	values[6]	values[4]	130	1			T37	9		T152	26		T236	10
auto[1]	values[6]	values[5]	205	1			T15	5		T23	12		T249	15
auto[1]	values[6]	values[6]	129	1			T30	5		T32	8		T34	46
auto[1]	values[6]	values[7]	114	1			T96	9		T38	10		T60	8
auto[1]	values[7]	values[0]	172	1			T176	14		T226	16		T157	9
auto[1]	values[7]	values[1]	170	1			T39	11		T152	20		T173	11
auto[1]	values[7]	values[2]	170	1			T174	15		T192	5		T243	7
auto[1]	values[7]	values[3]	123	1			T30	4		T39	10		T174	5
auto[1]	values[7]	values[4]	122	1			T188	11		T203	3		T154	12
auto[1]	values[7]	values[5]	125	1			T34	45		T38	4		T224	6
auto[1]	values[7]	values[6]	116	1			T37	23		T193	7		T232	10
auto[1]	values[7]	values[7]	182	1			T175	69		T174	5		T221	7