Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	342	1			T15	4		T31	1		T32	7
auto[ReadAddrCrossIntoMailbox]	258	1			T15	4		T32	5		T184	4
auto[ReadAddrCrossOutOfMailbox]	277	1			T11	2		T15	6		T30	1
auto[ReadAddrCrossAllMailbox]	204	1			T15	4		T32	4		T189	2
auto[ReadAddrOutsideMailbox]	3156	1			T11	2		T20	2		T15	37

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2161

1

T11

2

T20

1

T15

29

auto[1]

2076

1

T11

2

T20

1

T15

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	683	1			T15	9		T31	5		T30	2
read_ops[0x0b]	712	1			T20	2		T15	13		T31	6
read_ops[0x3b]	681	1			T15	7		T31	2		T30	3
read_ops[0x6b]	729	1			T15	5		T29	2		T31	2
read_ops[0xbb]	703	1			T11	2		T15	11		T31	2
read_ops[0xeb]	729	1			T11	2		T15	10		T31	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T199	1		T152	1		T188	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T31	1		T199	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T184	1		T62	2		T192	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T184	1		T152	2		T62	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T34	1		T173	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T15	1		T32	1		T203	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T173	1		T174	1		T154	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T15	1		T37	1		T60	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T15	6		T31	3		T30	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T15	1		T31	1		T32	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T39	1		T63	1		T186	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T32	1		T39	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T39	2		T152	1		T175	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T32	1		T175	1		T243	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T15	2		T30	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T34	1		T215	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T15	1		T32	1		T152	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T34	2		T39	1		T175	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T20	1		T15	7		T31	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T20	1		T15	3		T31	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T187	1		T199	1		T39	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T15	1		T32	2		T187	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T184	1		T152	1		T173	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T15	1		T184	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T174	1		T221	1		T156	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T32	1		T34	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T34	1		T39	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T175	1		T221	1		T207	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T15	1		T30	3		T32	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	239	1			T15	4		T31	2		T32	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T32	1		T39	1		T220	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T220	1		T173	1		T59	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T32	2		T39	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T15	1		T188	1		T292	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T34	1		T152	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T38	1		T186	1		T192	4
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T32	1		T189	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T189	1		T192	1		T207	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T15	1		T29	1		T31	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T15	3		T29	1		T30	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T15	2		T32	1		T34	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T96	3		T39	2		T152	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T15	1		T34	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T32	2		T174	1		T60	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T11	1		T15	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T11	1		T39	1		T300	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T15	1		T32	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T34	1		T175	2		T207	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T15	1		T31	2		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T15	5		T30	1		T32	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T15	1		T58	1		T63	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T32	2		T96	2		T58	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T15	1		T34	3		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T34	1		T39	1		T152	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T15	1		T39	2		T152	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T15	1		T32	1		T34	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T34	2		T39	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T15	1		T32	1		T37	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T11	1		T15	2		T31	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T11	1		T15	3		T30	2