Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2674899	1			T1	1		T2	1044		T3	1
all_pins[1]	2674899	1			T1	1		T2	1044		T3	1
all_pins[2]	2674899	1			T1	1		T2	1044		T3	1
all_pins[3]	2674899	1			T1	1		T2	1044		T3	1
all_pins[4]	2674899	1			T1	1		T2	1044		T3	1
all_pins[5]	2674899	1			T1	1		T2	1044		T3	1
all_pins[6]	2674899	1			T1	1		T2	1044		T3	1
all_pins[7]	2674899	1			T1	1		T2	1044		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21375313	1			T1	8		T2	8352		T3	8
values[0x1]	23879	1			T16	25		T35	8		T72	26
transitions[0x0=>0x1]	23277	1			T16	19		T35	8		T72	19
transitions[0x1=>0x0]	23286	1			T16	19		T35	8		T72	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2674279	1			T1	1		T2	1044		T3	1
all_pins[0]	values[0x1]	620	1			T16	3		T73	2		T170	4
all_pins[0]	transitions[0x0=>0x1]	344	1			T16	2		T170	3		T151	2
all_pins[0]	transitions[0x1=>0x0]	176	1			T16	3		T35	2		T72	4
all_pins[1]	values[0x0]	2674447	1			T1	1		T2	1044		T3	1
all_pins[1]	values[0x1]	452	1			T16	4		T35	2		T72	4
all_pins[1]	transitions[0x0=>0x1]	403	1			T16	4		T35	2		T72	3
all_pins[1]	transitions[0x1=>0x0]	282	1			T16	2		T72	1		T73	98
all_pins[2]	values[0x0]	2674568	1			T1	1		T2	1044		T3	1
all_pins[2]	values[0x1]	331	1			T16	2		T72	2		T73	100
all_pins[2]	transitions[0x0=>0x1]	262	1			T16	1		T72	1		T73	100
all_pins[2]	transitions[0x1=>0x0]	135	1			T16	4		T35	1		T72	1
all_pins[3]	values[0x0]	2674695	1			T1	1		T2	1044		T3	1
all_pins[3]	values[0x1]	204	1			T16	5		T35	1		T72	2
all_pins[3]	transitions[0x0=>0x1]	161	1			T16	4		T35	1		T72	1
all_pins[3]	transitions[0x1=>0x0]	145	1			T35	2		T72	3		T73	4
all_pins[4]	values[0x0]	2674711	1			T1	1		T2	1044		T3	1
all_pins[4]	values[0x1]	188	1			T16	1		T35	2		T72	4
all_pins[4]	transitions[0x0=>0x1]	145	1			T35	2		T72	3		T73	3
all_pins[4]	transitions[0x1=>0x0]	1651	1			T16	5		T35	1		T72	3
all_pins[5]	values[0x0]	2673205	1			T1	1		T2	1044		T3	1
all_pins[5]	values[0x1]	1694	1			T16	6		T35	1		T72	4
all_pins[5]	transitions[0x0=>0x1]	1645	1			T16	5		T35	1		T72	2
all_pins[5]	transitions[0x1=>0x0]	20167	1			T16	1		T35	2		T72	3
all_pins[6]	values[0x0]	2654683	1			T1	1		T2	1044		T3	1
all_pins[6]	values[0x1]	20216	1			T16	2		T35	2		T72	5
all_pins[6]	transitions[0x0=>0x1]	20182	1			T16	2		T35	2		T72	4
all_pins[6]	transitions[0x1=>0x0]	140	1			T16	2		T72	4		T73	7
all_pins[7]	values[0x0]	2674725	1			T1	1		T2	1044		T3	1
all_pins[7]	values[0x1]	174	1			T16	2		T72	5		T73	7
all_pins[7]	transitions[0x0=>0x1]	135	1			T16	1		T72	5		T73	6
all_pins[7]	transitions[0x1=>0x0]	590	1			T16	2		T73	1		T170	4