Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3455	1			T8	4		T9	4		T11	4
values[1]	3077	1			T15	20		T30	20		T32	20
values[2]	3506	1			T15	103		T32	40		T181	10
values[3]	4145	1			T15	20		T31	20		T30	34
values[4]	3287	1			T15	41		T31	20		T32	27
values[5]	3419	1			T15	61		T33	4		T30	30
values[6]	3486	1			T4	4		T28	27		T29	2
values[7]	3228	1			T15	74		T30	20		T32	25

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3010	1			T4	4		T15	103		T31	20
values[1]	3923	1			T11	4		T15	77		T30	30
values[2]	3588	1			T9	4		T20	8		T15	43
values[3]	3415	1			T15	40		T30	20		T32	40
values[4]	3631	1			T15	52		T32	20		T182	24
values[5]	3667	1			T15	20		T28	27		T30	31
values[6]	3650	1			T8	4		T15	20		T33	4
values[7]	2719	1			T31	20		T34	53		T37	35

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27167

1

T4

4

T8

4

T9

4

auto[1]

436

1

T15

4

T30

5

T32

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[7]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	384	1			T32	20		T39	47		T183	12
auto[0]	values[0]	values[1]	478	1			T11	4		T15	36		T97	12
auto[0]	values[0]	values[2]	463	1			T9	4		T20	8		T152	29
auto[0]	values[0]	values[3]	449	1			T184	6		T185	24		T186	22
auto[0]	values[0]	values[4]	552	1			T96	20		T34	91		T152	20
auto[0]	values[0]	values[5]	342	1			T32	20		T187	18		T34	56
auto[0]	values[0]	values[6]	470	1			T8	4		T39	39		T173	46
auto[0]	values[0]	values[7]	264	1			T173	20		T188	22		T156	49
auto[0]	values[1]	values[0]	259	1			T38	40		T152	20		T175	64
auto[0]	values[1]	values[1]	615	1			T32	20		T38	28		T175	25
auto[0]	values[1]	values[2]	467	1			T189	2		T96	20		T37	20
auto[0]	values[1]	values[3]	325	1			T30	20		T34	25		T190	12
auto[0]	values[1]	values[4]	479	1			T15	20		T60	31		T191	8
auto[0]	values[1]	values[5]	247	1			T174	39		T192	25		T193	20
auto[0]	values[1]	values[6]	372	1			T194	14		T174	26		T195	16
auto[0]	values[1]	values[7]	262	1			T58	12		T192	19		T196	18
auto[0]	values[2]	values[0]	318	1			T15	100		T175	20		T174	21
auto[0]	values[2]	values[1]	592	1			T175	20		T173	33		T197	135
auto[0]	values[2]	values[2]	511	1			T35	22		T38	24		T198	2
auto[0]	values[2]	values[3]	598	1			T32	20		T199	10		T200	2
auto[0]	values[2]	values[4]	443	1			T32	20		T201	31		T186	34
auto[0]	values[2]	values[5]	180	1			T47	16		T34	26		T39	23
auto[0]	values[2]	values[6]	590	1			T181	10		T188	20		T63	14
auto[0]	values[2]	values[7]	214	1			T37	33		T202	66		T133	39
auto[0]	values[3]	values[0]	475	1			T203	25		T154	17		T204	20
auto[0]	values[3]	values[1]	482	1			T34	75		T205	2		T175	103
auto[0]	values[3]	values[2]	318	1			T34	19		T36	2		T38	19
auto[0]	values[3]	values[3]	546	1			T175	80		T206	20		T207	42
auto[0]	values[3]	values[4]	531	1			T182	24		T37	35		T60	20
auto[0]	values[3]	values[5]	873	1			T15	20		T96	90		T60	25
auto[0]	values[3]	values[6]	455	1			T30	33		T34	30		T208	12
auto[0]	values[3]	values[7]	394	1			T31	20		T175	41		T173	50
auto[0]	values[4]	values[0]	248	1			T57	10		T209	22		T210	14
auto[0]	values[4]	values[1]	335	1			T15	20		T32	26		T60	20
auto[0]	values[4]	values[2]	678	1			T15	21		T31	20		T38	28
auto[0]	values[4]	values[3]	254	1			T98	8		T176	20		T207	23
auto[0]	values[4]	values[4]	281	1			T175	35		T173	20		T94	6
auto[0]	values[4]	values[5]	587	1			T87	6		T34	36		T37	39
auto[0]	values[4]	values[6]	556	1			T211	4		T38	21		T175	21
auto[0]	values[4]	values[7]	294	1			T152	20		T175	20		T212	24
auto[0]	values[5]	values[0]	407	1			T32	20		T173	33		T213	2
auto[0]	values[5]	values[1]	409	1			T15	21		T30	30		T32	21
auto[0]	values[5]	values[2]	343	1			T32	20		T214	12		T39	23
auto[0]	values[5]	values[3]	431	1			T15	40		T32	20		T215	2
auto[0]	values[5]	values[4]	347	1			T175	24		T174	22		T203	20
auto[0]	values[5]	values[5]	448	1			T34	20		T39	29		T60	76
auto[0]	values[5]	values[6]	476	1			T33	4		T188	20		T186	32
auto[0]	values[5]	values[7]	516	1			T174	32		T203	20		T155	20
auto[0]	values[6]	values[0]	391	1			T4	4		T31	20		T34	27
auto[0]	values[6]	values[1]	581	1			T37	20		T188	25		T60	20
auto[0]	values[6]	values[2]	339	1			T159	2		T37	20		T186	21
auto[0]	values[6]	values[3]	520	1			T171	26		T153	20		T216	24
auto[0]	values[6]	values[4]	428	1			T217	8		T34	22		T39	22
auto[0]	values[6]	values[5]	520	1			T28	27		T30	29		T206	17
auto[0]	values[6]	values[6]	315	1			T29	2		T218	8		T219	2
auto[0]	values[6]	values[7]	330	1			T220	8		T152	42		T203	21
auto[0]	values[7]	values[0]	484	1			T37	40		T174	20		T221	20
auto[0]	values[7]	values[1]	382	1			T37	20		T175	52		T173	33
auto[0]	values[7]	values[2]	425	1			T15	22		T222	10		T223	60
auto[0]	values[7]	values[3]	235	1			T174	20		T224	20		T221	20
auto[0]	values[7]	values[4]	506	1			T15	32		T35	20		T38	45
auto[0]	values[7]	values[5]	401	1			T37	20		T225	2		T60	21
auto[0]	values[7]	values[6]	360	1			T15	19		T30	18		T32	25
auto[0]	values[7]	values[7]	392	1			T34	53		T174	20		T188	20
auto[1]	values[0]	values[0]	3	1			T188	1		T226	2		-	-
auto[1]	values[0]	values[1]	9	1			T32	1		T227	1		T228	2
auto[1]	values[0]	values[2]	8	1			T229	2		T221	1		T202	1
auto[1]	values[0]	values[3]	6	1			T186	2		T156	1		T230	2
auto[1]	values[0]	values[4]	7	1			T152	1		T176	1		T231	4
auto[1]	values[0]	values[5]	8	1			T34	1		T186	4		T232	1
auto[1]	values[0]	values[6]	8	1			T39	1		T173	2		T233	1
auto[1]	values[0]	values[7]	4	1			T156	1		T24	1		T230	2
auto[1]	values[1]	values[0]	6	1			T175	1		T232	1		T234	4
auto[1]	values[1]	values[1]	2	1			T235	2		-	-		-	-
auto[1]	values[1]	values[2]	5	1			T236	1		T237	1		T238	3
auto[1]	values[1]	values[3]	12	1			T39	1		T158	1		T239	3
auto[1]	values[1]	values[4]	8	1			T60	3		T240	1		T241	2
auto[1]	values[1]	values[5]	7	1			T174	1		T192	1		T242	1
auto[1]	values[1]	values[6]	6	1			T243	1		T232	1		T244	2
auto[1]	values[1]	values[7]	5	1			T192	1		T158	2		T231	2
auto[1]	values[2]	values[0]	9	1			T15	3		T157	1		T245	2
auto[1]	values[2]	values[1]	2	1			T227	1		T246	1		-	-
auto[1]	values[2]	values[2]	6	1			T35	1		T38	1		T202	2
auto[1]	values[2]	values[3]	13	1			T40	4		T221	1		T23	2
auto[1]	values[2]	values[4]	10	1			T242	2		T233	3		T247	2
auto[1]	values[2]	values[5]	1	1			T241	1		-	-		-	-
auto[1]	values[2]	values[6]	12	1			T23	3		T54	5		T234	1
auto[1]	values[2]	values[7]	7	1			T37	2		T133	5		-	-
auto[1]	values[3]	values[0]	5	1			T154	3		T202	1		T131	1
auto[1]	values[3]	values[1]	11	1			T34	1		T246	5		T248	1
auto[1]	values[3]	values[2]	8	1			T34	1		T36	2		T38	1
auto[1]	values[3]	values[3]	10	1			T207	1		T243	1		T249	1
auto[1]	values[3]	values[4]	15	1			T37	1		T224	2		T207	2
auto[1]	values[3]	values[5]	6	1			T60	1		T202	3		T238	1
auto[1]	values[3]	values[6]	10	1			T30	1		T34	1		T250	6
auto[1]	values[3]	values[7]	6	1			T173	1		T60	2		T251	1
auto[1]	values[4]	values[0]	3	1			T243	2		T202	1		-	-
auto[1]	values[4]	values[1]	5	1			T32	1		T157	2		T158	1
auto[1]	values[4]	values[2]	12	1			T152	2		T192	1		T229	3
auto[1]	values[4]	values[3]	3	1			T156	1		T252	1		T253	1
auto[1]	values[4]	values[4]	6	1			T206	2		T24	2		T232	1
auto[1]	values[4]	values[5]	14	1			T34	1		T152	2		T173	1
auto[1]	values[4]	values[6]	6	1			T38	1		T174	1		T156	1
auto[1]	values[4]	values[7]	5	1			T186	2		T221	1		T254	2
auto[1]	values[5]	values[0]	9	1			T173	2		T255	4		T23	1
auto[1]	values[5]	values[1]	3	1			T243	2		T256	1		-	-
auto[1]	values[5]	values[2]	1	1			T230	1		-	-		-	-
auto[1]	values[5]	values[3]	4	1			T232	1		T54	1		T257	1
auto[1]	values[5]	values[5]	10	1			T39	3		T60	2		T193	2
auto[1]	values[5]	values[6]	2	1			T258	2		-	-		-	-
auto[1]	values[5]	values[7]	13	1			T155	3		T259	1		T260	3
auto[1]	values[6]	values[0]	6	1			T192	1		T261	2		T238	3
auto[1]	values[6]	values[1]	11	1			T188	1		T207	1		T24	2
auto[1]	values[6]	values[2]	4	1			T158	1		T262	2		T263	1
auto[1]	values[6]	values[3]	5	1			T241	1		T254	1		T234	2
auto[1]	values[6]	values[4]	8	1			T34	2		T229	2		T236	1
auto[1]	values[6]	values[5]	15	1			T30	2		T206	3		T156	1
auto[1]	values[6]	values[6]	2	1			T252	2		-	-		-	-
auto[1]	values[6]	values[7]	11	1			T152	4		T192	2		T158	1
auto[1]	values[7]	values[0]	3	1			T227	1		T131	2		-	-
auto[1]	values[7]	values[1]	6	1			T249	1		T158	3		T264	1
auto[1]	values[7]	values[3]	4	1			T221	1		T158	1		T202	1
auto[1]	values[7]	values[4]	10	1			T38	1		T265	2		T241	3
auto[1]	values[7]	values[5]	8	1			T245	2		T266	2		T267	1
auto[1]	values[7]	values[6]	10	1			T15	1		T30	2		T156	3
auto[1]	values[7]	values[7]	2	1			T268	2		-	-		-	-