Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1851

1

T1

4

T3

23

T5

7

auto[1]

1742

1

T1

6

T3

19

T5

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T5

9

T6

6

T12

6

auto[1]

1639

1

T1

10

T3

42

T12

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2845

1

T1

10

T3

42

T5

5

auto[1]

748

1

T5

4

T6

2

T12

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	694	1			T1	1		T3	8		T5	2
valid[1]	694	1			T1	4		T3	5		T5	1
valid[2]	754	1			T1	2		T3	10		T5	3
valid[3]	765	1			T1	2		T3	7		T5	2
valid[4]	686	1			T1	1		T3	12		T5	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	102	1			T5	1		T16	1		T50	2
auto[0]	auto[0]	valid[0]	auto[1]	174	1			T1	1		T3	5		T313	3
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T5	1		T43	2		T91	1
auto[0]	auto[0]	valid[1]	auto[1]	172	1			T1	1		T3	2		T15	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T12	1		T15	1		T16	1
auto[0]	auto[0]	valid[2]	auto[1]	189	1			T1	1		T3	7		T42	1
auto[0]	auto[0]	valid[3]	auto[0]	151	1			T5	1		T12	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	180	1			T1	1		T3	1		T18	2
auto[0]	auto[0]	valid[4]	auto[0]	114	1			T6	1		T50	2		T70	3
auto[0]	auto[0]	valid[4]	auto[1]	177	1			T3	8		T15	1		T32	1
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T50	2		T316	1		T92	2
auto[0]	auto[1]	valid[0]	auto[1]	152	1			T3	3		T15	1		T18	1
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T6	1		T12	1		T16	1
auto[0]	auto[1]	valid[1]	auto[1]	151	1			T1	3		T3	3		T18	2
auto[0]	auto[1]	valid[2]	auto[0]	137	1			T5	1		T6	2		T50	2
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T1	1		T3	3		T18	1
auto[0]	auto[1]	valid[3]	auto[0]	134	1			T5	1		T16	2		T43	2
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T1	1		T3	6		T12	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T43	1		T32	1		T92	1
auto[0]	auto[1]	valid[4]	auto[1]	131	1			T1	1		T3	4		T44	1
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T5	1		T91	1		T70	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T31	1		T70	2		T318	1
auto[1]	auto[0]	valid[2]	auto[0]	60	1			T5	2		T6	2		T12	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T43	1		T50	1		T92	3
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T5	1		T12	1		T92	1
auto[1]	auto[1]	valid[0]	auto[0]	87	1			T16	2		T50	3		T32	3
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T32	1		T70	2		T81	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T81	2		T161	1		T72	3
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T43	2		T70	2		T81	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T12	1		T15	1		T43	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal