Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48430

1

T5

208

T6

206

T12

151

auto[1]

18194

1

T1

10

T3

437

T12

31

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48981

1

T1

10

T3

437

T5

142

auto[1]

17643

1

T5

66

T6

71

T12

66

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34594	1			T1	10		T3	226		T5	115
others[1]	5448	1			T3	35		T5	15		T6	23
others[2]	5741	1			T3	33		T5	16		T6	16
others[3]	6342	1			T3	42		T5	27		T6	17
interest[1]	3556	1			T3	23		T5	6		T6	10
interest[4]	22515	1			T1	10		T3	141		T5	71
interest[64]	10943	1			T3	78		T5	29		T6	41

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15909	1			T5	80		T6	68		T12	42
auto[0]	auto[0]	others[1]	2503	1			T5	11		T6	19		T12	12
auto[0]	auto[0]	others[2]	2654	1			T5	11		T6	9		T12	8
auto[0]	auto[0]	others[3]	2976	1			T5	17		T6	11		T12	7
auto[0]	auto[0]	interest[1]	1690	1			T5	5		T6	6		T12	5
auto[0]	auto[0]	interest[4]	10349	1			T5	51		T6	42		T12	25
auto[0]	auto[0]	interest[64]	5055	1			T5	18		T6	22		T12	11
auto[0]	auto[1]	others[0]	9509	1			T1	10		T3	226		T12	16
auto[0]	auto[1]	others[1]	1507	1			T3	35		T12	3		T15	1
auto[0]	auto[1]	others[2]	1560	1			T3	33		T12	2		T15	2
auto[0]	auto[1]	others[3]	1744	1			T3	42		T12	3		T15	6
auto[0]	auto[1]	interest[1]	922	1			T3	23		T12	4		T15	1
auto[0]	auto[1]	interest[4]	6243	1			T1	10		T3	141		T12	13
auto[0]	auto[1]	interest[64]	2952	1			T3	78		T12	3		T15	2
auto[1]	auto[0]	others[0]	9176	1			T5	35		T6	31		T12	31
auto[1]	auto[0]	others[1]	1438	1			T5	4		T6	4		T12	6
auto[1]	auto[0]	others[2]	1527	1			T5	5		T6	7		T12	7
auto[1]	auto[0]	others[3]	1622	1			T5	10		T6	6		T12	5
auto[1]	auto[0]	interest[1]	944	1			T5	1		T6	4		T12	4
auto[1]	auto[0]	interest[4]	5923	1			T5	20		T6	18		T12	22
auto[1]	auto[0]	interest[64]	2936	1			T5	11		T6	19		T12	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal