Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	831	1			T16	17		T35	4		T72	14
all_values[1]	831	1			T16	17		T35	4		T72	14
all_values[2]	831	1			T16	17		T35	4		T72	14
all_values[3]	831	1			T16	17		T35	4		T72	14
all_values[4]	831	1			T16	17		T35	4		T72	14
all_values[5]	831	1			T16	17		T35	4		T72	14
all_values[6]	831	1			T16	17		T35	4		T72	14
all_values[7]	831	1			T16	17		T35	4		T72	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3572

1

T16

82

T35

24

T72

48

auto[1]

3076

1

T16

54

T35

8

T72

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2651

1

T16

63

T35

14

T72

45

auto[1]

3997

1

T16

73

T35

18

T72

67

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3797

1

T16

83

T35

19

T72

65

auto[1]

2851

1

T16

53

T35

13

T72

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	179	1			T16	2		T35	4		T72	2
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T16	2		T72	4		T73	2
all_values[0]	auto[0]	auto[1]	auto[0]	163	1			T16	5		T72	3		T73	2
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T16	2		T73	2		T170	3
all_values[0]	auto[1]	auto[0]	auto[1]	196	1			T16	5		T72	4		T73	5
all_values[0]	auto[1]	auto[1]	auto[1]	137	1			T16	1		T72	1		T73	2
all_values[1]	auto[0]	auto[0]	auto[0]	156	1			T16	5		T35	2		T72	1
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T16	2		T72	1		T73	4
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T16	4		T72	5		T170	4
all_values[1]	auto[0]	auto[1]	auto[1]	101	1			T16	2		T35	1		T72	1
all_values[1]	auto[1]	auto[0]	auto[1]	177	1			T16	1		T35	1		T72	2
all_values[1]	auto[1]	auto[1]	auto[1]	176	1			T16	3		T72	4		T73	4
all_values[2]	auto[0]	auto[0]	auto[0]	180	1			T16	6		T35	1		T72	1
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T16	3		T35	1		T72	5
all_values[2]	auto[0]	auto[1]	auto[0]	117	1			T16	3		T72	4		T152	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T73	4		T170	2		T151	2
all_values[2]	auto[1]	auto[0]	auto[1]	197	1			T16	2		T35	2		T72	3
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T16	3		T72	1		T73	4
all_values[3]	auto[0]	auto[0]	auto[0]	171	1			T16	5		T35	2		T72	1
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T72	1		T73	1
all_values[3]	auto[0]	auto[1]	auto[0]	154	1			T16	4		T35	1		T72	6
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T16	2		T72	1		T73	1
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T16	3		T72	4		T73	1
all_values[3]	auto[1]	auto[1]	auto[1]	162	1			T16	2		T35	1		T72	1
all_values[4]	auto[0]	auto[0]	auto[0]	152	1			T16	5		T73	3		T170	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T16	1		T72	1		T73	1
all_values[4]	auto[0]	auto[1]	auto[0]	171	1			T16	4		T72	4		T73	2
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T35	1		T72	1		T73	2
all_values[4]	auto[1]	auto[0]	auto[1]	191	1			T16	4		T35	3		T72	4
all_values[4]	auto[1]	auto[1]	auto[1]	156	1			T16	3		T72	4		T73	3
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T16	4		T72	2		T73	4
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T16	1		T35	3		T72	6
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T16	8		T35	1		T72	3
all_values[5]	auto[1]	auto[1]	auto[1]	175	1			T16	4		T72	3		T73	4
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T16	3		T35	1		T72	3
all_values[6]	auto[0]	auto[0]	auto[1]	94	1			T16	3		T73	4		T170	2
all_values[6]	auto[0]	auto[1]	auto[0]	115	1			T16	3		T72	3		T73	3
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T35	1		T72	2		T151	2
all_values[6]	auto[1]	auto[0]	auto[1]	224	1			T16	6		T35	2		T72	3
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T16	2		T72	3		T73	3
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T16	6		T73	4		T170	5
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T35	1		T72	1		T152	2
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T16	3		T72	4		T170	3
all_values[7]	auto[0]	auto[1]	auto[1]	61	1			T16	2		T72	2		T73	4
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T16	5		T35	3		T72	2
all_values[7]	auto[1]	auto[1]	auto[1]	171	1			T16	1		T72	5		T73	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal