Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2537998	1			T1	1		T2	2532		T3	1
all_values[1]	2537998	1			T1	1		T2	2532		T3	1
all_values[2]	2537998	1			T1	1		T2	2532		T3	1
all_values[3]	2537998	1			T1	1		T2	2532		T3	1
all_values[4]	2537998	1			T1	1		T2	2532		T3	1
all_values[5]	2537998	1			T1	1		T2	2532		T3	1
all_values[6]	2537998	1			T1	1		T2	2532		T3	1
all_values[7]	2537998	1			T1	1		T2	2532		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19966561

1

T1

8

T2

20256

T3

8

auto[1]

337423

1

T9

16116

T55

6845

T56

103

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20282742

1

T1

8

T2

20256

T3

8

auto[1]

21242

1

T5

2

T9

299

T11

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2526641	1			T1	1		T2	2532		T3	1
all_values[0]	auto[0]	auto[1]	10922	1			T5	1		T9	104		T12	61
all_values[0]	auto[1]	auto[0]	242	1			T9	3		T55	1		T56	7
all_values[0]	auto[1]	auto[1]	193	1			T9	7		T55	7		T56	3
all_values[1]	auto[0]	auto[0]	2499820	1			T1	1		T2	2532		T3	1
all_values[1]	auto[0]	auto[1]	5320	1			T5	1		T9	89		T12	57
all_values[1]	auto[1]	auto[0]	32596	1			T9	3209		T55	4		T56	11
all_values[1]	auto[1]	auto[1]	262	1			T9	3		T55	6		T56	4
all_values[2]	auto[0]	auto[0]	2462427	1			T1	1		T2	2532		T3	1
all_values[2]	auto[0]	auto[1]	2001	1			T9	44		T12	7		T17	15
all_values[2]	auto[1]	auto[0]	73246	1			T9	3207		T55	3395		T56	5
all_values[2]	auto[1]	auto[1]	324	1			T9	9		T55	5		T56	7
all_values[3]	auto[0]	auto[0]	2448877	1			T1	1		T2	2532		T3	1
all_values[3]	auto[0]	auto[1]	199	1			T55	3		T56	3		T165	4
all_values[3]	auto[1]	auto[0]	88694	1			T9	3213		T55	6		T56	6
all_values[3]	auto[1]	auto[1]	228	1			T9	4		T55	3		T56	7
all_values[4]	auto[0]	auto[0]	2516027	1			T1	1		T2	2532		T3	1
all_values[4]	auto[0]	auto[1]	205	1			T9	2		T55	2		T56	6
all_values[4]	auto[1]	auto[0]	21561	1			T9	3212		T55	3		T56	5
all_values[4]	auto[1]	auto[1]	205	1			T9	8		T55	7		T56	5
all_values[5]	auto[0]	auto[0]	2522263	1			T1	1		T2	2532		T3	1
all_values[5]	auto[0]	auto[1]	334	1			T9	5		T11	1		T35	1
all_values[5]	auto[1]	auto[0]	15217	1			T9	9		T55	6		T56	6
all_values[5]	auto[1]	auto[1]	184	1			T9	2		T55	2		T56	7
all_values[6]	auto[0]	auto[0]	2453178	1			T1	1		T2	2532		T3	1
all_values[6]	auto[0]	auto[1]	227	1			T9	7		T55	1		T56	7
all_values[6]	auto[1]	auto[0]	84397	1			T9	6		T55	3389		T56	11
all_values[6]	auto[1]	auto[1]	196	1			T9	4		T55	5		T56	5
all_values[7]	auto[0]	auto[0]	2517881	1			T1	1		T2	2532		T3	1
all_values[7]	auto[0]	auto[1]	239	1			T9	3		T55	8		T56	8
all_values[7]	auto[1]	auto[0]	19675	1			T9	3212		T55	3		T56	8
all_values[7]	auto[1]	auto[1]	203	1			T9	8		T55	3		T56	6