Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33845	1			T2	190		T4	268		T5	336
auto[SpiFlashAddrCfg]	6813	1			T2	42		T4	28		T5	51
auto[SpiFlashAddr3b]	8126	1			T2	39		T4	41		T5	68
auto[SpiFlashAddr4b]	6766	1			T2	18		T4	26		T5	60

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31332

1

T2

91

T4

139

T5

309

auto[1]

24218

1

T2

198

T4

224

T5

206

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29166

1

T2

112

T4

282

T5

167

auto[1]

26384

1

T2

177

T4

81

T5

348

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37974	1			T2	208		T4	298		T5	369
values[1]	927	1			T2	4		T4	2		T5	3
values[2]	1330	1			T2	6		T4	6		T5	14
values[3]	1378	1			T2	8		T4	7		T5	19
values[4]	1245	1			T2	4		T4	4		T5	10
values[5]	1374	1			T2	9		T4	4		T5	18
values[6]	1383	1			T2	5		T4	10		T5	8
values[7]	1275	1			T2	7		T4	7		T5	10
values[8]	8664	1			T2	38		T4	25		T5	64

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30285

1

T2

289

T5

515

T6

2

auto[1]

25265

1

T4

363

T12

189

T13

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53551

1

T2

283

T4

348

T5

502

write

1999

1

T2

6

T4

15

T5

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17828

1

T2

70

T4

85

T5

133

valids[0x1]

37722

1

T2

219

T4

278

T5

382

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1330	1			T2	11		T4	7		T5	10
internal_process_ops[0x5a]	1414	1			T2	6		T4	6		T5	13
internal_process_ops[0x05]	21402	1			T2	139		T4	196		T5	262
internal_process_ops[0x35]	1376	1			T2	4		T4	7		T5	10
internal_process_ops[0x15]	1391	1			T2	1		T4	9		T5	5
internal_process_ops[0x03]	960	1			T2	11		T4	3		T5	9
internal_process_ops[0x0b]	954	1			T2	8		T4	3		T5	9
internal_process_ops[0x3b]	992	1			T2	5		T5	13		T9	8
internal_process_ops[0x6b]	926	1			T2	8		T4	1		T5	5
internal_process_ops[0xbb]	957	1			T2	5		T5	11		T9	8
internal_process_ops[0xeb]	970	1			T2	4		T5	9		T9	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54544

1

T2

283

T4

351

T5

506

auto[1]

1006

1

T2

6

T4

12

T5

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53609

1

T2

283

T4

350

T5

502

auto[1]

1941

1

T2

6

T4

13

T5

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10451

1

T2

36

T5

213

T9

59

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6857

1

T2

154

T5

122

T9

26

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2053

1

T2

24

T5

31

T9

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1742

1

T2

14

T5

15

T6

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2376

1

T2

21

T5

35

T9

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2098

1

T2

16

T5

32

T9

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1942

1

T2

9

T5

28

T9

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1794

1

T2

9

T5

26

T9

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

60

1

T15

2

T28

1

T30

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

55

1

T9

1

T31

1

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

64

1

T5

1

T9

3

T30

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T15

2

T30

2

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

59

1

T5

1

T9

2

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T2

1

T26

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

57

1

T15

2

T28

4

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

52

1

T2

3

T5

4

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

64

1

T15

3

T26

1

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

49

1

T28

1

T30

8

T20

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

50

1

T28

1

T29

2

T166

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T2

2

T5

1

T9

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

91

1

T15

1

T28

4

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

61

1

T5

1

T28

1

T29

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

47

1

T5

2

T15

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

61

1

T5

3

T15

3

T28

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9218

1

T4

88

T12

78

T17

73

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6786

1

T4

176

T12

24

T17

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1292

1

T4

14

T12

9

T17

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1231

1

T4

10

T12

17

T17

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1602

1

T4

21

T12

20

T13

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1557

1

T4

13

T12

15

T17

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1351

1

T4

8

T12

7

T13

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1201

1

T4

18

T12

13

T17

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

70

1

T34

1

T73

1

T20

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

69

1

T4

2

T73

1

T75

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T12

3

T17

2

T73

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

72

1

T4

2

T34

2

T55

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

65

1

T4

1

T17

1

T34

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T4

3

T12

1

T17

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T34

2

T167

1

T20

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

47

1

T34

4

T167

1

T75

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

70

1

T12

2

T34

2

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T4

2

T17

5

T73

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

55

1

T4

2

T73

2

T55

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

53

1

T4

3

T55

2

T75

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

53

1

T20

1

T74

3

T168

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T167

2

T74

3

T55

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

39

1

T55

3

T36

1

T169

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

67

1

T34

1

T73

2

T74

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3847	1			T2	28		T5	48		T9	37
auto[0]	values[0]	valids[0x1]	15995	1			T2	180		T5	321		T7	2
auto[0]	values[1]	valids[0x1]	521	1			T2	4		T5	3		T9	5
auto[0]	values[2]	valids[0x0]	549	1			T2	4		T5	10		T9	4
auto[0]	values[2]	valids[0x1]	249	1			T2	2		T5	4		T15	1
auto[0]	values[3]	valids[0x0]	534	1			T2	7		T5	9		T9	4
auto[0]	values[3]	valids[0x1]	286	1			T2	1		T5	10		T9	2
auto[0]	values[4]	valids[0x0]	525	1			T2	2		T5	5		T9	3
auto[0]	values[4]	valids[0x1]	260	1			T2	2		T5	5		T9	1
auto[0]	values[5]	valids[0x0]	482	1			T2	6		T5	13		T9	7
auto[0]	values[5]	valids[0x1]	306	1			T2	3		T5	5		T9	5
auto[0]	values[6]	valids[0x0]	510	1			T2	3		T5	1		T6	2
auto[0]	values[6]	valids[0x1]	322	1			T2	2		T5	7		T15	3
auto[0]	values[7]	valids[0x0]	480	1			T2	5		T5	7		T9	6
auto[0]	values[7]	valids[0x1]	304	1			T2	2		T5	3		T9	4
auto[0]	values[8]	valids[0x0]	3270	1			T2	15		T5	40		T9	38
auto[0]	values[8]	valids[0x1]	1845	1			T2	23		T5	24		T9	15
auto[1]	values[0]	valids[0x0]	3619	1			T4	51		T12	41		T17	40
auto[1]	values[0]	valids[0x1]	14513	1			T4	247		T12	71		T13	1
auto[1]	values[1]	valids[0x1]	406	1			T4	2		T12	3		T17	4
auto[1]	values[2]	valids[0x0]	313	1			T4	4		T12	5		T17	2
auto[1]	values[2]	valids[0x1]	219	1			T4	2		T12	2		T17	3
auto[1]	values[3]	valids[0x0]	328	1			T4	6		T13	1		T17	6
auto[1]	values[3]	valids[0x1]	230	1			T4	1		T12	8		T34	3
auto[1]	values[4]	valids[0x0]	291	1			T4	2		T12	3		T34	4
auto[1]	values[4]	valids[0x1]	169	1			T4	2		T12	3		T17	1
auto[1]	values[5]	valids[0x0]	347	1			T4	1		T12	2		T17	2
auto[1]	values[5]	valids[0x1]	239	1			T4	3		T12	2		T17	1
auto[1]	values[6]	valids[0x0]	321	1			T4	3		T12	4		T17	3
auto[1]	values[6]	valids[0x1]	230	1			T4	7		T12	2		T17	3
auto[1]	values[7]	valids[0x0]	281	1			T4	2		T12	9		T17	3
auto[1]	values[7]	valids[0x1]	210	1			T4	5		T12	1		T17	1
auto[1]	values[8]	valids[0x0]	2131	1			T4	16		T12	20		T13	1
auto[1]	values[8]	valids[0x1]	1418	1			T4	9		T12	13		T13	1