Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2810125

1

T2

6612

T4

16510

T5

23510

auto[1]

20045

1

T2

129

T4

183

T5

255

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714918

1

T2

48

T4

55

T5

80

auto[1]

2115252

1

T2

6693

T4

16638

T5

23685

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	526756	1			T2	3		T4	514		T5	1147
auto[524288:1048575]	347044	1			T2	7		T4	736		T5	612
auto[1048576:1572863]	356943	1			T2	535		T4	1070		T12	911
auto[1572864:2097151]	336338	1			T2	891		T4	6305		T5	27
auto[2097152:2621439]	307370	1			T2	4470		T4	63		T5	4691
auto[2621440:3145727]	272941	1			T2	12		T4	4602		T5	6677
auto[3145728:3670015]	356391	1			T2	694		T4	3351		T5	1153
auto[3670016:4194303]	326387	1			T2	129		T4	52		T5	9458

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2135378

1

T2

6736

T4

16684

T5

23763

auto[1]

694792

1

T2

5

T4

9

T5

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2422165

1

T2

6741

T4

9809

T5

18532

auto[1]

408005

1

T4

6884

T5

5233

T9

3658

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	183210	1			T2	3		T4	1		T5	15
auto[0]	auto[0]	auto[0:524287]	auto[1]	298914	1			T4	512		T5	824		T9	586
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	83919	1			T2	2		T4	2		T5	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	227185	1			T2	5		T4	701		T5	520
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	83045	1			T2	4		T4	7		T12	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	217637	1			T2	523		T4	1031		T12	512
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	81636	1			T2	5		T5	8		T9	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	167558	1			T2	871		T5	1		T9	259
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	54755	1			T2	10		T4	8		T5	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	201316	1			T2	4399		T4	45		T5	4612
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	62374	1			T2	12		T4	14		T5	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	170357	1			T4	3959		T5	3698		T9	1960
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	77064	1			T2	5		T4	1		T5	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225896	1			T2	644		T4	3349		T5	1150
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	79240	1			T2	1		T4	3		T5	9
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	191404	1			T2	128		T4	7		T5	7407
auto[0]	auto[1]	auto[0:524287]	auto[0]	289	1			T4	1		T5	1		T9	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	41030	1			T5	256		T9	3		T15	2437
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	735	1			T9	3		T15	2		T28	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	33026	1			T12	2703		T73	4		T29	131
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1572	1			T12	3		T15	4		T28	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51943	1			T12	395		T15	7		T28	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1112	1			T4	1		T9	4		T15	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	83550	1			T4	6304		T9	1919		T28	3116
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1659	1			T17	1		T30	2		T29	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47645	1			T30	1		T29	110		T167	646
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	563	1			T4	3		T5	1		T9	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	36676	1			T4	560		T5	2934		T9	1711
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	673	1			T4	1		T12	2		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50504	1			T12	1024		T15	958		T28	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1127	1			T9	2		T82	1		T28	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52511	1			T5	2041		T28	1		T17	555
auto[1]	auto[0]	auto[0:524287]	auto[0]	275	1			T5	3		T12	1		T28	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2657	1			T5	48		T28	35		T17	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	188	1			T4	1		T5	3		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1555	1			T4	32		T5	81		T15	22
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	222	1			T2	1		T4	3		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2209	1			T2	7		T4	29		T15	72
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	210	1			T2	1		T5	1		T9	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1836	1			T2	14		T5	17		T9	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	159	1			T2	2		T4	1		T5	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1381	1			T2	59		T4	9		T5	65
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	202	1			T4	5		T5	3		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2103	1			T4	47		T5	31		T15	45
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	169	1			T2	2		T9	1		T15	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1649	1			T2	43		T15	13		T17	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	158	1			T4	2		T5	1		T15	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1682	1			T4	40		T15	4		T34	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	45	1			T9	1		T20	1		T74	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	336	1			T9	11		T74	7		T166	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	43	1			T73	2		T29	3		T20	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	393	1			T73	57		T29	2		T20	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	49	1			T15	3		T26	3		T73	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	266	1			T15	17		T26	34		T73	17
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	47	1			T9	1		T160	1		T168	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	389	1			T160	2		T168	5		T150	19
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	34	1			T30	1		T167	1		T20	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	421	1			T30	24		T167	3		T169	27
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	62	1			T4	1		T34	1		T31	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	604	1			T4	13		T34	16		T31	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	46	1			T28	1		T55	2		T36	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	390	1			T28	7		T55	38		T36	18
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	36	1			T28	1		T26	1		T167	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	229	1			T28	5		T26	26		T167	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1716592	1			T2	6610		T4	9636		T5	18275
auto[0]	auto[0]	auto[1]	688918	1			T2	2		T4	4		T5	2
auto[0]	auto[1]	auto[0]	399174	1			T4	6869		T5	5233		T9	3645
auto[0]	auto[1]	auto[1]	5441	1			T4	1		T15	2		T26	2
auto[1]	auto[0]	auto[0]	16309	1			T2	126		T4	165		T5	255
auto[1]	auto[0]	auto[1]	346	1			T2	3		T4	4		T15	1
auto[1]	auto[1]	auto[0]	3303	1			T4	14		T9	12		T15	19
auto[1]	auto[1]	auto[1]	87	1			T9	1		T15	1		T28	1