Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17324

1

T2

91

T5

309

T9

108

auto[1]

12961

1

T2

198

T5

206

T6

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3551	1			T2	20		T5	40		T9	20
values[1]	3845	1			T6	2		T9	20		T30	241
values[2]	3889	1			T5	170		T9	30		T15	166
values[3]	3664	1			T5	73		T9	41		T82	28
values[4]	4197	1			T2	20		T5	40		T9	32
values[5]	3629	1			T2	178		T5	26		T9	21
values[6]	3403	1			T2	71		T9	20		T15	20
values[7]	4107	1			T5	166		T7	2		T9	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3336	1			T5	73		T14	20		T15	89
values[1]	4252	1			T2	62		T5	105		T6	2
values[2]	3631	1			T2	100		T5	66		T7	2
values[3]	3406	1			T2	20		T5	20		T9	20
values[4]	3805	1			T2	107		T5	168		T15	166
values[5]	4025	1			T5	20		T15	71		T28	93
values[6]	4004	1			T5	43		T9	20		T15	22
values[7]	3826	1			T5	20		T9	41		T15	146

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	168	1			T15	78		T28	12		T228	2
auto[0]	values[0]	values[1]	404	1			T26	12		T229	2		T230	61
auto[0]	values[0]	values[2]	116	1			T15	13		T31	14		T20	9
auto[0]	values[0]	values[3]	251	1			T2	14		T5	11		T15	14
auto[0]	values[0]	values[4]	293	1			T15	22		T30	8		T187	6
auto[0]	values[0]	values[5]	266	1			T5	14		T29	15		T31	16
auto[0]	values[0]	values[6]	258	1			T28	48		T231	2		T150	10
auto[0]	values[0]	values[7]	261	1			T9	12		T30	13		T224	12
auto[0]	values[1]	values[0]	199	1			T30	8		T232	8		T166	13
auto[0]	values[1]	values[1]	307	1			T9	10		T30	13		T26	21
auto[0]	values[1]	values[2]	309	1			T26	57		T185	19		T150	11
auto[0]	values[1]	values[3]	268	1			T213	8		T150	7		T194	19
auto[0]	values[1]	values[4]	302	1			T30	101		T26	29		T190	10
auto[0]	values[1]	values[5]	263	1			T26	11		T160	8		T208	8
auto[0]	values[1]	values[6]	212	1			T183	15		T166	20		T55	18
auto[0]	values[1]	values[7]	232	1			T26	11		T188	13		T189	2
auto[0]	values[2]	values[0]	272	1			T175	12		T180	12		T193	11
auto[0]	values[2]	values[1]	269	1			T9	10		T26	14		T182	9
auto[0]	values[2]	values[2]	309	1			T28	29		T95	4		T30	10
auto[0]	values[2]	values[3]	160	1			T185	26		T233	6		T160	15
auto[0]	values[2]	values[4]	491	1			T5	139		T28	12		T166	18
auto[0]	values[2]	values[5]	188	1			T15	14		T166	24		T216	8
auto[0]	values[2]	values[6]	313	1			T5	11		T26	5		T166	25
auto[0]	values[2]	values[7]	182	1			T15	8		T182	12		T234	20
auto[0]	values[3]	values[0]	182	1			T5	44		T28	15		T20	16
auto[0]	values[3]	values[1]	245	1			T184	12		T151	10		T193	39
auto[0]	values[3]	values[2]	291	1			T5	9		T82	28		T186	10
auto[0]	values[3]	values[3]	310	1			T28	5		T29	7		T183	16
auto[0]	values[3]	values[4]	199	1			T30	11		T20	10		T183	10
auto[0]	values[3]	values[5]	293	1			T26	12		T20	12		T185	15
auto[0]	values[3]	values[6]	376	1			T9	9		T28	106		T20	14
auto[0]	values[3]	values[7]	435	1			T9	7		T31	13		T44	2
auto[0]	values[4]	values[0]	373	1			T235	18		T180	13		T151	11
auto[0]	values[4]	values[1]	126	1			T28	10		T31	26		T186	9
auto[0]	values[4]	values[2]	294	1			T5	14		T9	23		T31	20
auto[0]	values[4]	values[3]	219	1			T31	12		T160	20		T206	8
auto[0]	values[4]	values[4]	366	1			T2	11		T5	9		T15	93
auto[0]	values[4]	values[5]	354	1			T28	14		T123	14		T183	11
auto[0]	values[4]	values[6]	368	1			T15	10		T55	18		T180	26
auto[0]	values[4]	values[7]	225	1			T236	8		T237	45		T200	10
auto[0]	values[5]	values[0]	258	1			T30	48		T31	12		T187	12
auto[0]	values[5]	values[1]	130	1			T2	12		T9	13		T26	15
auto[0]	values[5]	values[2]	284	1			T2	8		T5	9		T15	28
auto[0]	values[5]	values[3]	358	1			T238	10		T183	14		T55	10
auto[0]	values[5]	values[4]	209	1			T2	28		T28	44		T178	10
auto[0]	values[5]	values[5]	615	1			T15	22		T239	12		T29	15
auto[0]	values[5]	values[6]	246	1			T123	10		T166	11		T240	10
auto[0]	values[5]	values[7]	253	1			T30	60		T31	8		T241	10
auto[0]	values[6]	values[0]	354	1			T226	18		T55	7		T186	19
auto[0]	values[6]	values[1]	279	1			T2	9		T9	10		T30	14
auto[0]	values[6]	values[2]	162	1			T2	9		T220	6		T188	19
auto[0]	values[6]	values[3]	249	1			T217	11		T188	15		T242	10
auto[0]	values[6]	values[4]	129	1			T20	11		T243	12		T244	6
auto[0]	values[6]	values[5]	338	1			T15	7		T28	8		T26	8
auto[0]	values[6]	values[6]	194	1			T245	20		T151	13		T193	16
auto[0]	values[6]	values[7]	203	1			T30	12		T185	10		T183	10
auto[0]	values[7]	values[0]	139	1			T5	17		T29	10		T150	5
auto[0]	values[7]	values[1]	344	1			T5	11		T166	8		T186	13
auto[0]	values[7]	values[2]	319	1			T30	26		T31	7		T55	10
auto[0]	values[7]	values[3]	249	1			T9	14		T185	15		T246	16
auto[0]	values[7]	values[4]	393	1			T15	12		T20	11		T128	24
auto[0]	values[7]	values[5]	128	1			T247	6		T180	13		T150	16
auto[0]	values[7]	values[6]	275	1			T5	11		T30	12		T179	24
auto[0]	values[7]	values[7]	267	1			T5	10		T30	9		T26	15
auto[1]	values[0]	values[0]	67	1			T15	11		T28	8		T219	17
auto[1]	values[0]	values[1]	252	1			T26	42		T206	20		T37	10
auto[1]	values[0]	values[2]	59	1			T15	9		T31	6		T20	11
auto[1]	values[0]	values[3]	142	1			T2	6		T5	9		T15	11
auto[1]	values[0]	values[4]	270	1			T15	7		T30	12		T187	22
auto[1]	values[0]	values[5]	177	1			T5	6		T29	6		T31	10
auto[1]	values[0]	values[6]	279	1			T28	15		T248	18		T150	12
auto[1]	values[0]	values[7]	288	1			T9	8		T30	72		T185	13
auto[1]	values[1]	values[0]	356	1			T30	50		T166	7		T182	8
auto[1]	values[1]	values[1]	388	1			T6	2		T9	10		T30	62
auto[1]	values[1]	values[2]	154	1			T26	19		T185	4		T150	9
auto[1]	values[1]	values[3]	245	1			T86	16		T150	48		T194	93
auto[1]	values[1]	values[4]	76	1			T30	7		T26	11		T130	11
auto[1]	values[1]	values[5]	251	1			T26	23		T160	12		T249	8
auto[1]	values[1]	values[6]	204	1			T183	7		T166	25		T55	61
auto[1]	values[1]	values[7]	79	1			T26	9		T188	11		T250	6
auto[1]	values[2]	values[0]	129	1			T180	9		T193	9		T225	49
auto[1]	values[2]	values[1]	175	1			T9	20		T26	6		T32	12
auto[1]	values[2]	values[2]	409	1			T28	6		T30	101		T217	4
auto[1]	values[2]	values[3]	124	1			T185	15		T160	5		T182	12
auto[1]	values[2]	values[4]	207	1			T5	9		T28	8		T166	7
auto[1]	values[2]	values[5]	132	1			T15	6		T166	3		T216	12
auto[1]	values[2]	values[6]	141	1			T5	11		T26	32		T166	7
auto[1]	values[2]	values[7]	388	1			T15	138		T182	10		T222	60
auto[1]	values[3]	values[0]	74	1			T5	9		T28	5		T20	7
auto[1]	values[3]	values[1]	160	1			T184	8		T151	10		T193	8
auto[1]	values[3]	values[2]	205	1			T5	11		T186	10		T206	6
auto[1]	values[3]	values[3]	201	1			T28	15		T29	21		T183	5
auto[1]	values[3]	values[4]	124	1			T30	9		T20	12		T183	10
auto[1]	values[3]	values[5]	117	1			T26	8		T251	2		T20	12
auto[1]	values[3]	values[6]	300	1			T9	11		T28	10		T20	6
auto[1]	values[3]	values[7]	152	1			T9	14		T31	7		T184	5
auto[1]	values[4]	values[0]	248	1			T14	20		T180	7		T151	9
auto[1]	values[4]	values[1]	284	1			T28	10		T31	18		T186	77
auto[1]	values[4]	values[2]	173	1			T5	6		T9	9		T31	5
auto[1]	values[4]	values[3]	187	1			T31	8		T160	5		T252	10
auto[1]	values[4]	values[4]	247	1			T2	9		T5	11		T15	13
auto[1]	values[4]	values[5]	244	1			T28	20		T253	12		T123	6
auto[1]	values[4]	values[6]	207	1			T15	12		T85	2		T254	6
auto[1]	values[4]	values[7]	282	1			T200	10		T255	12		T223	8
auto[1]	values[5]	values[0]	79	1			T30	9		T31	8		T187	8
auto[1]	values[5]	values[1]	161	1			T2	30		T9	8		T26	5
auto[1]	values[5]	values[2]	189	1			T2	41		T5	17		T15	3
auto[1]	values[5]	values[3]	89	1			T183	8		T55	10		T184	8
auto[1]	values[5]	values[4]	248	1			T2	59		T28	6		T180	28
auto[1]	values[5]	values[5]	166	1			T15	9		T29	5		T211	7
auto[1]	values[5]	values[6]	231	1			T123	16		T166	9		T240	29
auto[1]	values[5]	values[7]	113	1			T30	12		T31	12		T256	8
auto[1]	values[6]	values[0]	267	1			T126	24		T55	13		T186	10
auto[1]	values[6]	values[1]	155	1			T2	11		T9	10		T30	6
auto[1]	values[6]	values[2]	134	1			T2	42		T188	5		T206	3
auto[1]	values[6]	values[3]	145	1			T217	10		T188	5		T150	13
auto[1]	values[6]	values[4]	50	1			T20	10		T151	12		T21	7
auto[1]	values[6]	values[5]	248	1			T15	13		T28	51		T26	26
auto[1]	values[6]	values[6]	233	1			T151	7		T193	9		T216	12
auto[1]	values[6]	values[7]	263	1			T30	54		T124	14		T185	10
auto[1]	values[7]	values[0]	171	1			T5	3		T29	10		T150	15
auto[1]	values[7]	values[1]	573	1			T5	94		T166	12		T186	77
auto[1]	values[7]	values[2]	224	1			T7	2		T30	6		T31	13
auto[1]	values[7]	values[3]	209	1			T9	6		T185	6		T180	55
auto[1]	values[7]	values[4]	201	1			T15	19		T20	9		T183	13
auto[1]	values[7]	values[5]	245	1			T177	18		T180	18		T150	4
auto[1]	values[7]	values[6]	167	1			T5	10		T30	8		T20	7
auto[1]	values[7]	values[7]	203	1			T5	10		T30	11		T26	5