Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15314

1

T2

174

T5

277

T6

1

auto[1]

40236

1

T2

115

T4

363

T5

238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1163	1			T2	13		T4	7		T5	9
auto[4:7]	24278	1			T2	147		T4	217		T5	278
auto[8:11]	1141	1			T2	8		T4	3		T5	9
auto[12:15]	265	1			T2	1		T5	3		T9	2
auto[16:19]	291	1			T2	6		T4	2		T5	3
auto[20:23]	1606	1			T2	1		T4	10		T5	5
auto[24:27]	273	1			T4	3		T28	1		T30	3
auto[28:31]	312	1			T4	1		T12	2		T28	1
auto[32:35]	305	1			T2	2		T4	3		T5	4
auto[36:39]	294	1			T2	2		T4	1		T12	5
auto[40:43]	334	1			T4	2		T5	7		T12	3
auto[44:47]	274	1			T4	4		T5	1		T9	2
auto[48:51]	284	1			T2	1		T12	1		T15	2
auto[52:55]	1593	1			T2	4		T4	7		T5	14
auto[56:59]	1195	1			T2	5		T5	13		T9	9
auto[60:63]	283	1			T2	2		T4	1		T15	3
auto[64:67]	283	1			T2	1		T4	6		T5	6
auto[68:71]	311	1			T4	2		T9	3		T12	1
auto[72:75]	301	1			T4	1		T12	3		T15	1
auto[76:79]	287	1			T5	1		T9	2		T12	1
auto[80:83]	308	1			T4	1		T15	1		T28	4
auto[84:87]	308	1			T2	3		T5	1		T9	5
auto[88:91]	1614	1			T2	7		T4	9		T5	13
auto[92:95]	273	1			T2	2		T4	2		T5	4
auto[96:99]	281	1			T2	3		T9	5		T15	1
auto[100:103]	280	1			T2	2		T4	1		T5	4
auto[104:107]	1136	1			T2	9		T4	1		T5	8
auto[108:111]	301	1			T4	4		T9	2		T12	3
auto[112:115]	321	1			T4	1		T15	3		T28	3
auto[116:119]	275	1			T2	1		T5	2		T9	3
auto[120:123]	326	1			T2	1		T4	1		T5	2
auto[124:127]	292	1			T5	2		T12	1		T15	2
auto[128:131]	313	1			T2	1		T4	2		T5	1
auto[132:135]	308	1			T2	1		T4	3		T5	2
auto[136:139]	281	1			T4	1		T9	3		T12	1
auto[140:143]	277	1			T5	4		T6	2		T9	3
auto[144:147]	270	1			T5	4		T9	1		T14	2
auto[148:151]	276	1			T5	1		T9	2		T12	1
auto[152:155]	306	1			T5	3		T9	2		T15	1
auto[156:159]	1542	1			T2	12		T4	7		T5	10
auto[160:163]	311	1			T4	7		T5	8		T12	1
auto[164:167]	284	1			T4	2		T5	2		T9	1
auto[168:171]	264	1			T2	3		T4	2		T5	3
auto[172:175]	256	1			T2	3		T4	1		T5	3
auto[176:179]	284	1			T2	1		T5	8		T9	2
auto[180:183]	1568	1			T2	7		T4	13		T5	5
auto[184:187]	1193	1			T2	5		T5	11		T9	9
auto[188:191]	284	1			T2	3		T5	5		T12	1
auto[192:195]	331	1			T4	1		T5	3		T9	3
auto[196:199]	271	1			T2	3		T5	4		T9	1
auto[200:203]	261	1			T4	3		T9	1		T15	2
auto[204:207]	286	1			T2	2		T4	1		T5	2
auto[208:211]	266	1			T2	1		T5	1		T9	1
auto[212:215]	288	1			T2	2		T4	1		T5	4
auto[216:219]	243	1			T5	2		T9	3		T12	1
auto[220:223]	321	1			T2	2		T4	1		T5	1
auto[224:227]	315	1			T2	1		T4	6		T9	1
auto[228:231]	241	1			T4	4		T5	4		T9	2
auto[232:235]	2494	1			T2	12		T4	8		T5	18
auto[236:239]	271	1			T4	1		T5	3		T12	3
auto[240:243]	282	1			T2	2		T4	1		T5	5
auto[244:247]	291	1			T2	2		T4	6		T5	1
auto[248:251]	301	1			T2	3		T4	1		T5	5
auto[252:255]	283	1			T2	2		T4	1		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	446	1			T2	6		T5	7		T9	3
auto[0:3]	auto[1]	717	1			T2	7		T4	7		T5	2
auto[4:7]	auto[0]	6538	1			T2	97		T5	171		T9	22
auto[4:7]	auto[1]	17740	1			T2	50		T4	217		T5	107
auto[8:11]	auto[0]	380	1			T2	4		T5	5		T7	1
auto[8:11]	auto[1]	761	1			T2	4		T4	3		T5	4
auto[12:15]	auto[0]	77	1			T2	1		T5	2		T9	2
auto[12:15]	auto[1]	188	1			T5	1		T15	1		T17	1
auto[16:19]	auto[0]	80	1			T2	5		T5	1		T28	1
auto[16:19]	auto[1]	211	1			T2	1		T4	2		T5	2
auto[20:23]	auto[0]	429	1			T2	1		T5	2		T9	1
auto[20:23]	auto[1]	1177	1			T4	10		T5	3		T9	6
auto[24:27]	auto[0]	75	1			T28	1		T30	2		T31	1
auto[24:27]	auto[1]	198	1			T4	3		T30	1		T26	4
auto[28:31]	auto[0]	77	1			T28	1		T30	2		T26	1
auto[28:31]	auto[1]	235	1			T4	1		T12	2		T17	3
auto[32:35]	auto[0]	85	1			T2	1		T9	1		T28	4
auto[32:35]	auto[1]	220	1			T2	1		T4	3		T5	4
auto[36:39]	auto[0]	84	1			T2	2		T30	1		T26	1
auto[36:39]	auto[1]	210	1			T4	1		T12	5		T28	3
auto[40:43]	auto[0]	84	1			T15	1		T30	3		T253	3
auto[40:43]	auto[1]	250	1			T4	2		T5	7		T12	3
auto[44:47]	auto[0]	77	1			T5	1		T9	2		T15	1
auto[44:47]	auto[1]	197	1			T4	4		T28	1		T17	2
auto[48:51]	auto[0]	72	1			T2	1		T15	1		T30	1
auto[48:51]	auto[1]	212	1			T12	1		T15	1		T28	1
auto[52:55]	auto[0]	436	1			T2	2		T5	11		T9	7
auto[52:55]	auto[1]	1157	1			T2	2		T4	7		T5	3
auto[56:59]	auto[0]	407	1			T2	1		T5	3		T9	6
auto[56:59]	auto[1]	788	1			T2	4		T5	10		T9	3
auto[60:63]	auto[0]	72	1			T15	3		T30	4		T26	2
auto[60:63]	auto[1]	211	1			T2	2		T4	1		T28	1
auto[64:67]	auto[0]	53	1			T2	1		T185	2		T232	1
auto[64:67]	auto[1]	230	1			T4	6		T5	6		T9	1
auto[68:71]	auto[0]	84	1			T9	3		T15	1		T30	2
auto[68:71]	auto[1]	227	1			T4	2		T12	1		T15	1
auto[72:75]	auto[0]	80	1			T30	1		T239	1		T31	2
auto[72:75]	auto[1]	221	1			T4	1		T12	3		T15	1
auto[76:79]	auto[0]	69	1			T5	1		T9	2		T15	1
auto[76:79]	auto[1]	218	1			T12	1		T17	1		T34	1
auto[80:83]	auto[0]	74	1			T15	1		T30	2		T26	1
auto[80:83]	auto[1]	234	1			T4	1		T28	4		T17	1
auto[84:87]	auto[0]	73	1			T2	3		T30	3		T26	1
auto[84:87]	auto[1]	235	1			T5	1		T9	5		T12	2
auto[88:91]	auto[0]	439	1			T2	6		T5	2		T9	2
auto[88:91]	auto[1]	1175	1			T2	1		T4	9		T5	11
auto[92:95]	auto[0]	77	1			T14	1		T15	5		T28	4
auto[92:95]	auto[1]	196	1			T2	2		T4	2		T5	4
auto[96:99]	auto[0]	59	1			T2	1		T9	2		T28	4
auto[96:99]	auto[1]	222	1			T2	2		T9	3		T15	1
auto[100:103]	auto[0]	65	1			T2	2		T9	1		T14	2
auto[100:103]	auto[1]	215	1			T4	1		T5	4		T12	4
auto[104:107]	auto[0]	402	1			T2	4		T5	5		T9	4
auto[104:107]	auto[1]	734	1			T2	5		T4	1		T5	3
auto[108:111]	auto[0]	66	1			T15	3		T26	2		T226	1
auto[108:111]	auto[1]	235	1			T4	4		T9	2		T12	3
auto[112:115]	auto[0]	89	1			T15	3		T28	2		T29	1
auto[112:115]	auto[1]	232	1			T4	1		T28	1		T17	4
auto[116:119]	auto[0]	65	1			T9	1		T15	1		T217	2
auto[116:119]	auto[1]	210	1			T2	1		T5	2		T9	2
auto[120:123]	auto[0]	84	1			T5	2		T28	1		T30	2
auto[120:123]	auto[1]	242	1			T2	1		T4	1		T9	1
auto[124:127]	auto[0]	70	1			T5	1		T15	1		T28	6
auto[124:127]	auto[1]	222	1			T5	1		T12	1		T15	1
auto[128:131]	auto[0]	70	1			T9	2		T15	1		T28	4
auto[128:131]	auto[1]	243	1			T2	1		T4	2		T5	1
auto[132:135]	auto[0]	65	1			T15	1		T28	1		T26	1
auto[132:135]	auto[1]	243	1			T2	1		T4	3		T5	2
auto[136:139]	auto[0]	83	1			T9	1		T31	3		T249	1
auto[136:139]	auto[1]	198	1			T4	1		T9	2		T12	1
auto[140:143]	auto[0]	70	1			T5	1		T6	1		T9	3
auto[140:143]	auto[1]	207	1			T5	3		T6	1		T14	1
auto[144:147]	auto[0]	62	1			T5	3		T9	1		T14	1
auto[144:147]	auto[1]	208	1			T5	1		T14	1		T15	1
auto[148:151]	auto[0]	79	1			T5	1		T9	2		T28	1
auto[148:151]	auto[1]	197	1			T12	1		T15	1		T28	2
auto[152:155]	auto[0]	75	1			T15	1		T28	2		T30	3
auto[152:155]	auto[1]	231	1			T5	3		T9	2		T30	1
auto[156:159]	auto[0]	423	1			T2	11		T5	5		T9	2
auto[156:159]	auto[1]	1119	1			T2	1		T4	7		T5	5
auto[160:163]	auto[0]	84	1			T5	6		T15	1		T86	1
auto[160:163]	auto[1]	227	1			T4	7		T5	2		T12	1
auto[164:167]	auto[0]	66	1			T15	2		T31	2		T20	3
auto[164:167]	auto[1]	218	1			T4	2		T5	2		T9	1
auto[168:171]	auto[0]	67	1			T5	2		T9	2		T28	2
auto[168:171]	auto[1]	197	1			T2	3		T4	2		T5	1
auto[172:175]	auto[0]	59	1			T2	3		T5	1		T15	3
auto[172:175]	auto[1]	197	1			T4	1		T5	2		T12	3
auto[176:179]	auto[0]	76	1			T5	6		T9	1		T15	5
auto[176:179]	auto[1]	208	1			T2	1		T5	2		T9	1
auto[180:183]	auto[0]	393	1			T2	1		T5	1		T9	1
auto[180:183]	auto[1]	1175	1			T2	6		T4	13		T5	4
auto[184:187]	auto[0]	429	1			T2	2		T5	5		T9	2
auto[184:187]	auto[1]	764	1			T2	3		T5	6		T9	7
auto[188:191]	auto[0]	73	1			T2	1		T5	3		T26	2
auto[188:191]	auto[1]	211	1			T2	2		T5	2		T12	1
auto[192:195]	auto[0]	77	1			T9	3		T30	1		T26	1
auto[192:195]	auto[1]	254	1			T4	1		T5	3		T12	1
auto[196:199]	auto[0]	86	1			T2	2		T5	4		T30	1
auto[196:199]	auto[1]	185	1			T2	1		T9	1		T12	1
auto[200:203]	auto[0]	57	1			T15	1		T29	1		T123	1
auto[200:203]	auto[1]	204	1			T4	3		T9	1		T15	1
auto[204:207]	auto[0]	65	1			T5	2		T28	3		T30	1
auto[204:207]	auto[1]	221	1			T2	2		T4	1		T9	1
auto[208:211]	auto[0]	82	1			T9	1		T28	2		T29	3
auto[208:211]	auto[1]	184	1			T2	1		T5	1		T12	1
auto[212:215]	auto[0]	70	1			T5	4		T15	3		T30	1
auto[212:215]	auto[1]	218	1			T2	2		T4	1		T9	1
auto[216:219]	auto[0]	79	1			T9	3		T14	2		T15	2
auto[216:219]	auto[1]	164	1			T5	2		T12	1		T14	2
auto[220:223]	auto[0]	79	1			T2	2		T15	1		T30	5
auto[220:223]	auto[1]	242	1			T4	1		T5	1		T9	1
auto[224:227]	auto[0]	75	1			T2	1		T9	1		T15	1
auto[224:227]	auto[1]	240	1			T4	6		T15	4		T34	3
auto[228:231]	auto[0]	54	1			T28	1		T26	1		T29	3
auto[228:231]	auto[1]	187	1			T4	4		T5	4		T9	2
auto[232:235]	auto[0]	792	1			T2	6		T5	12		T9	7
auto[232:235]	auto[1]	1702	1			T2	6		T4	8		T5	6
auto[236:239]	auto[0]	59	1			T15	1		T28	1		T30	2
auto[236:239]	auto[1]	212	1			T4	1		T5	3		T12	3
auto[240:243]	auto[0]	71	1			T2	2		T5	1		T9	2
auto[240:243]	auto[1]	211	1			T4	1		T5	4		T9	2
auto[244:247]	auto[0]	61	1			T2	1		T5	1		T9	1
auto[244:247]	auto[1]	230	1			T2	1		T4	6		T12	1
auto[248:251]	auto[0]	95	1			T2	2		T5	2		T9	3
auto[248:251]	auto[1]	206	1			T2	1		T4	1		T5	3
auto[252:255]	auto[0]	70	1			T2	2		T5	3		T9	1
auto[252:255]	auto[1]	213	1			T4	1		T9	1		T12	2