Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	361	1			T2	3		T5	10		T9	4
auto[ReadAddrCrossIntoMailbox]	258	1			T2	2		T5	6		T9	4
auto[ReadAddrCrossOutOfMailbox]	278	1			T2	4		T5	4		T9	2
auto[ReadAddrCrossAllMailbox]	201	1			T2	3		T5	4		T15	4
auto[ReadAddrOutsideMailbox]	3288	1			T2	29		T5	32		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T2

16

T5

30

T7

1

auto[1]

2208

1

T2

25

T5

26

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	738	1			T2	11		T5	9		T9	4
read_ops[0x0b]	727	1			T2	8		T5	9		T7	2
read_ops[0x3b]	761	1			T2	5		T5	13		T9	8
read_ops[0x6b]	695	1			T2	8		T5	5		T9	6
read_ops[0xbb]	731	1			T2	5		T5	11		T9	8
read_ops[0xeb]	734	1			T2	4		T5	9		T9	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T2	1		T5	1		T28	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T20	1		T240	1		T257	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T2	1		T15	1		T55	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T9	1		T15	2		T28	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T5	1		T9	1		T55	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T2	3		T15	4		T30	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T28	1		T95	1		T67	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T5	1		T95	1		T123	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T2	2		T5	5		T9	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T2	4		T5	1		T9	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T5	2		T28	1		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T5	1		T26	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T15	1		T28	2		T20	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T166	1		T184	1		T150	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T31	1		T20	1		T150	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T15	1		T31	1		T184	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T28	1		T26	1		T150	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T5	1		T15	1		T26	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T2	4		T5	3		T7	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T2	4		T5	2		T7	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T28	2		T26	2		T183	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T2	1		T5	2		T9	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T26	1		T123	1		T183	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T2	1		T5	2		T9	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T15	4		T31	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T5	2		T28	1		T185	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T20	1		T150	1		T258	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T2	1		T183	1		T166	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T2	1		T5	3		T9	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T2	1		T5	4		T9	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T9	1		T30	1		T184	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T15	1		T29	1		T123	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T5	1		T9	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T5	1		T15	2		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T15	2		T28	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T151	1		T193	2		T37	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T2	1		T15	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T2	1		T150	1		T211	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T2	2		T5	2		T9	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T2	4		T5	1		T9	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T5	1		T30	1		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T2	1		T5	1		T9	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T5	1		T20	1		T123	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T5	1		T9	1		T15	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T5	1		T182	2		T184	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T28	1		T186	1		T240	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T5	1		T160	1		T188	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T26	1		T185	1		T55	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T2	2		T5	1		T9	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T2	2		T5	4		T9	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T5	2		T26	1		T178	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T9	1		T15	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T15	1		T26	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T28	1		T20	1		T182	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T9	1		T28	1		T26	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T2	1		T15	2		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T5	1		T28	1		T259	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T15	2		T20	1		T150	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T2	2		T5	4		T9	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T2	1		T5	2		T9	4