Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2537998	1			T1	1		T2	2532		T3	1
all_pins[1]	2537998	1			T1	1		T2	2532		T3	1
all_pins[2]	2537998	1			T1	1		T2	2532		T3	1
all_pins[3]	2537998	1			T1	1		T2	2532		T3	1
all_pins[4]	2537998	1			T1	1		T2	2532		T3	1
all_pins[5]	2537998	1			T1	1		T2	2532		T3	1
all_pins[6]	2537998	1			T1	1		T2	2532		T3	1
all_pins[7]	2537998	1			T1	1		T2	2532		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20218476	1			T1	8		T2	20256		T3	8
values[0x1]	85508	1			T9	45		T55	3416		T56	44
transitions[0x0=>0x1]	85087	1			T9	28		T55	3406		T56	30
transitions[0x1=>0x0]	85102	1			T9	28		T55	3406		T56	30

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2537805	1			T1	1		T2	2532		T3	1
all_pins[0]	values[0x1]	193	1			T9	7		T55	7		T56	3
all_pins[0]	transitions[0x0=>0x1]	144	1			T9	6		T55	3		T56	3
all_pins[0]	transitions[0x1=>0x0]	245	1			T9	2		T55	2		T56	4
all_pins[1]	values[0x0]	2537704	1			T1	1		T2	2532		T3	1
all_pins[1]	values[0x1]	294	1			T9	3		T55	6		T56	4
all_pins[1]	transitions[0x0=>0x1]	245	1			T55	5		T56	4		T165	6
all_pins[1]	transitions[0x1=>0x0]	280	1			T9	6		T55	4		T56	7
all_pins[2]	values[0x0]	2537669	1			T1	1		T2	2532		T3	1
all_pins[2]	values[0x1]	329	1			T9	9		T55	5		T56	7
all_pins[2]	transitions[0x0=>0x1]	274	1			T9	7		T55	4		T56	3
all_pins[2]	transitions[0x1=>0x0]	173	1			T9	2		T55	2		T56	3
all_pins[3]	values[0x0]	2537770	1			T1	1		T2	2532		T3	1
all_pins[3]	values[0x1]	228	1			T9	4		T55	3		T56	7
all_pins[3]	transitions[0x0=>0x1]	164	1			T9	1		T55	1		T56	4
all_pins[3]	transitions[0x1=>0x0]	141	1			T9	5		T55	5		T56	2
all_pins[4]	values[0x0]	2537793	1			T1	1		T2	2532		T3	1
all_pins[4]	values[0x1]	205	1			T9	8		T55	7		T56	5
all_pins[4]	transitions[0x0=>0x1]	160	1			T9	7		T55	6		T56	3
all_pins[4]	transitions[0x1=>0x0]	249	1			T9	1		T55	1		T56	5
all_pins[5]	values[0x0]	2537704	1			T1	1		T2	2532		T3	1
all_pins[5]	values[0x1]	294	1			T9	2		T55	2		T56	7
all_pins[5]	transitions[0x0=>0x1]	249	1			T9	2		T55	1		T56	5
all_pins[5]	transitions[0x1=>0x0]	83717	1			T9	4		T55	3382		T56	3
all_pins[6]	values[0x0]	2454236	1			T1	1		T2	2532		T3	1
all_pins[6]	values[0x1]	83762	1			T9	4		T55	3383		T56	5
all_pins[6]	transitions[0x0=>0x1]	83705	1			T9	1		T55	3383		T56	4
all_pins[6]	transitions[0x1=>0x0]	146	1			T9	5		T55	3		T56	5
all_pins[7]	values[0x0]	2537795	1			T1	1		T2	2532		T3	1
all_pins[7]	values[0x1]	203	1			T9	8		T55	3		T56	6
all_pins[7]	transitions[0x0=>0x1]	146	1			T9	4		T55	3		T56	4
all_pins[7]	transitions[0x1=>0x0]	151	1			T9	3		T55	7		T56	1