Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4127	1			T2	138		T5	20		T7	2
values[1]	3454	1			T5	209		T9	30		T15	173
values[2]	3833	1			T2	49		T15	51		T28	55
values[3]	4318	1			T9	40		T30	108		T26	54
values[4]	3585	1			T2	62		T5	20		T9	32
values[5]	4397	1			T5	178		T9	41		T30	77
values[6]	3186	1			T2	20		T5	88		T6	2
values[7]	3385	1			T2	20		T9	41		T15	166

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2906	1			T2	40		T9	40		T28	35
values[1]	3511	1			T5	53		T6	2		T9	21
values[2]	3910	1			T2	67		T5	67		T7	2
values[3]	3450	1			T2	51		T5	20		T15	31
values[4]	3846	1			T5	40		T9	20		T15	157
values[5]	4532	1			T5	253		T9	20		T15	49
values[6]	3799	1			T2	49		T5	20		T9	32
values[7]	4331	1			T2	82		T5	62		T14	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29805

1

T2

283

T5

506

T6

2

auto[1]

480

1

T2

6

T5

9

T9

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	281	1			T2	18		T9	19		T26	20
auto[0]	values[0]	values[1]	331	1			T29	20		T55	20		T180	20
auto[0]	values[0]	values[2]	464	1			T2	65		T7	2		T160	20
auto[0]	values[0]	values[3]	361	1			T2	51		T166	25		T55	20
auto[0]	values[0]	values[4]	703	1			T15	104		T26	40		T217	21
auto[0]	values[0]	values[5]	367	1			T30	66		T123	26		T55	27
auto[0]	values[0]	values[6]	864	1			T28	158		T29	23		T20	20
auto[0]	values[0]	values[7]	678	1			T5	20		T26	39		T180	22
auto[0]	values[1]	values[0]	386	1			T224	12		T31	25		T185	21
auto[0]	values[1]	values[1]	309	1			T260	18		T29	21		T183	21
auto[0]	values[1]	values[2]	474	1			T5	20		T9	25		T15	31
auto[0]	values[1]	values[3]	349	1			T261	10		T194	20		T206	35
auto[0]	values[1]	values[4]	326	1			T5	20		T15	31		T30	56
auto[0]	values[1]	values[5]	820	1			T5	147		T15	20		T30	19
auto[0]	values[1]	values[6]	393	1			T5	20		T15	69		T183	20
auto[0]	values[1]	values[7]	352	1			T15	22		T28	19		T185	20
auto[0]	values[2]	values[0]	359	1			T28	35		T186	20		T262	20
auto[0]	values[2]	values[1]	388	1			T183	20		T188	21		T181	36
auto[0]	values[2]	values[2]	744	1			T15	21		T31	20		T256	8
auto[0]	values[2]	values[3]	400	1			T166	20		T160	25		T263	8
auto[0]	values[2]	values[4]	581	1			T28	20		T183	18		T166	32
auto[0]	values[2]	values[5]	440	1			T15	29		T186	84		T264	6
auto[0]	values[2]	values[6]	363	1			T2	49		T185	21		T244	6
auto[0]	values[2]	values[7]	508	1			T253	12		T265	83		T186	90
auto[0]	values[3]	values[0]	342	1			T9	20		T266	12		T150	40
auto[0]	values[3]	values[1]	535	1			T185	21		T55	20		T187	22
auto[0]	values[3]	values[2]	648	1			T9	20		T20	21		T267	4
auto[0]	values[3]	values[3]	315	1			T26	20		T228	2		T268	22
auto[0]	values[3]	values[4]	427	1			T128	24		T183	22		T246	16
auto[0]	values[3]	values[5]	968	1			T30	106		T166	24		T240	20
auto[0]	values[3]	values[6]	565	1			T26	34		T150	23		T151	18
auto[0]	values[3]	values[7]	451	1			T31	20		T269	12		T226	18
auto[0]	values[4]	values[0]	443	1			T26	34		T29	21		T32	10
auto[0]	values[4]	values[1]	427	1			T30	72		T194	96		T206	30
auto[0]	values[4]	values[2]	353	1			T5	16		T15	23		T20	20
auto[0]	values[4]	values[3]	567	1			T15	31		T30	85		T178	10
auto[0]	values[4]	values[4]	466	1			T15	20		T270	2		T271	18
auto[0]	values[4]	values[5]	396	1			T82	28		T31	20		T183	21
auto[0]	values[4]	values[6]	471	1			T9	32		T28	20		T183	22
auto[0]	values[4]	values[7]	416	1			T2	61		T30	75		T86	16
auto[0]	values[5]	values[0]	282	1			T251	2		T185	23		T180	20
auto[0]	values[5]	values[1]	616	1			T5	53		T9	21		T229	2
auto[0]	values[5]	values[2]	343	1			T185	19		T231	2		T180	28
auto[0]	values[5]	values[3]	334	1			T5	20		T31	23		T185	19
auto[0]	values[5]	values[4]	541	1			T9	20		T239	12		T20	21
auto[0]	values[5]	values[5]	846	1			T5	104		T30	20		T55	20
auto[0]	values[5]	values[6]	383	1			T30	53		T213	8		T182	20
auto[0]	values[5]	values[7]	980	1			T184	18		T272	16		T273	18
auto[0]	values[6]	values[0]	322	1			T238	10		T84	8		T184	46
auto[0]	values[6]	values[1]	357	1			T6	2		T30	18		T29	19
auto[0]	values[6]	values[2]	342	1			T5	26		T26	20		T20	20
auto[0]	values[6]	values[3]	508	1			T30	32		T20	43		T274	2
auto[0]	values[6]	values[4]	498	1			T5	20		T26	52		T180	20
auto[0]	values[6]	values[5]	193	1			T28	32		T29	21		T209	22
auto[0]	values[6]	values[6]	289	1			T28	20		T179	24		T123	20
auto[0]	values[6]	values[7]	612	1			T2	20		T5	40		T14	20
auto[0]	values[7]	values[0]	442	1			T2	19		T30	20		T232	8
auto[0]	values[7]	values[1]	478	1			T247	6		T240	39		T275	6
auto[0]	values[7]	values[2]	488	1			T9	20		T15	166		T26	37
auto[0]	values[7]	values[3]	565	1			T28	48		T30	109		T26	56
auto[0]	values[7]	values[4]	237	1			T28	57		T31	19		T217	21
auto[0]	values[7]	values[5]	452	1			T9	20		T28	41		T30	20
auto[0]	values[7]	values[6]	404	1			T95	4		T26	27		T123	20
auto[0]	values[7]	values[7]	262	1			T85	2		T254	6		T151	33
auto[1]	values[0]	values[0]	5	1			T2	2		T9	1		T188	1
auto[1]	values[0]	values[1]	11	1			T67	2		T250	1		T197	3
auto[1]	values[0]	values[2]	5	1			T2	2		T227	1		T219	2
auto[1]	values[0]	values[3]	2	1			T194	1		T276	1		-	-
auto[1]	values[0]	values[4]	10	1			T15	2		T277	2		T278	2
auto[1]	values[0]	values[5]	12	1			T186	2		T151	1		T200	5
auto[1]	values[0]	values[6]	15	1			T28	1		T29	5		T211	3
auto[1]	values[0]	values[7]	18	1			T26	1		T223	3		T201	5
auto[1]	values[1]	values[0]	8	1			T31	1		T188	3		T201	3
auto[1]	values[1]	values[1]	4	1			T29	2		T204	1		T279	1
auto[1]	values[1]	values[2]	8	1			T5	1		T9	5		T55	1
auto[1]	values[1]	values[3]	4	1			T223	1		T280	1		T281	2
auto[1]	values[1]	values[4]	5	1			T30	2		T206	2		T197	1
auto[1]	values[1]	values[5]	8	1			T5	1		T30	1		T180	1
auto[1]	values[1]	values[6]	2	1			T219	1		T282	1		-	-
auto[1]	values[1]	values[7]	6	1			T28	1		T248	2		T204	2
auto[1]	values[2]	values[0]	6	1			T223	2		T283	1		T284	1
auto[1]	values[2]	values[1]	6	1			T181	2		T223	1		T201	1
auto[1]	values[2]	values[2]	6	1			T15	1		T181	1		T201	1
auto[1]	values[2]	values[3]	11	1			T38	3		T285	6		T286	2
auto[1]	values[2]	values[4]	11	1			T183	2		T182	2		T184	1
auto[1]	values[2]	values[5]	3	1			T186	2		T287	1		-	-
auto[1]	values[2]	values[6]	2	1			T219	2		-	-		-	-
auto[1]	values[2]	values[7]	5	1			T193	1		T288	1		T289	2
auto[1]	values[3]	values[0]	6	1			T206	2		T276	4		-	-
auto[1]	values[3]	values[1]	11	1			T187	1		T194	1		T216	3
auto[1]	values[3]	values[2]	11	1			T194	1		T222	1		T290	1
auto[1]	values[3]	values[3]	3	1			T181	1		T291	2		-	-
auto[1]	values[3]	values[4]	5	1			T183	1		T37	3		T258	1
auto[1]	values[3]	values[5]	9	1			T30	2		T166	1		T223	2
auto[1]	values[3]	values[6]	15	1			T150	1		T151	2		T206	1
auto[1]	values[3]	values[7]	7	1			T222	2		T255	1		T204	1
auto[1]	values[4]	values[0]	10	1			T32	2		T201	2		T292	6
auto[1]	values[4]	values[1]	4	1			T206	1		T293	2		T279	1
auto[1]	values[4]	values[2]	7	1			T5	4		T15	2		T294	1
auto[1]	values[4]	values[3]	9	1			T188	1		T219	1		T294	1
auto[1]	values[4]	values[4]	7	1			T154	2		T195	4		T295	1
auto[1]	values[4]	values[5]	2	1			T183	1		T278	1		-	-
auto[1]	values[4]	values[6]	4	1			T250	2		T283	1		T296	1
auto[1]	values[4]	values[7]	3	1			T2	1		T37	1		T287	1
auto[1]	values[5]	values[0]	5	1			T205	1		T283	4		-	-
auto[1]	values[5]	values[1]	12	1			T20	3		T188	2		T180	3
auto[1]	values[5]	values[2]	5	1			T185	1		T297	1		T204	1
auto[1]	values[5]	values[3]	8	1			T185	2		T180	2		T67	2
auto[1]	values[5]	values[4]	11	1			T20	2		T184	3		T130	1
auto[1]	values[5]	values[5]	3	1			T5	1		T258	1		T290	1
auto[1]	values[5]	values[6]	14	1			T30	4		T215	8		T203	1
auto[1]	values[5]	values[7]	14	1			T184	2		T151	1		T21	1
auto[1]	values[6]	values[0]	7	1			T184	2		T288	3		T298	1
auto[1]	values[6]	values[1]	6	1			T30	2		T29	1		T38	3
auto[1]	values[6]	values[2]	8	1			T250	1		T195	2		T204	5
auto[1]	values[6]	values[3]	3	1			T20	1		T299	2		-	-
auto[1]	values[6]	values[4]	11	1			T26	2		T289	2		T280	4
auto[1]	values[6]	values[5]	9	1			T28	2		T29	1		T280	1
auto[1]	values[6]	values[6]	9	1			T150	2		T151	1		T154	1
auto[1]	values[6]	values[7]	12	1			T5	2		T154	2		T300	1
auto[1]	values[7]	values[0]	2	1			T2	1		T284	1		-	-
auto[1]	values[7]	values[1]	16	1			T151	1		T301	1		T277	1
auto[1]	values[7]	values[2]	4	1			T9	1		T197	2		T291	1
auto[1]	values[7]	values[3]	11	1			T28	2		T30	2		T197	3
auto[1]	values[7]	values[4]	7	1			T28	2		T31	1		T197	2
auto[1]	values[7]	values[5]	4	1			T28	1		T183	1		T206	1
auto[1]	values[7]	values[6]	6	1			T26	2		T150	1		T277	1
auto[1]	values[7]	values[7]	7	1			T225	2		T223	1		T282	1