Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1658

1

T1

13

T3

3

T5

2

auto[1]

1705

1

T1

12

T3

4

T5

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1721

1

T5

2

T9

11

T12

13

auto[1]

1642

1

T1

25

T3

7

T5

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2663

1

T1

25

T3

7

T5

1

auto[1]

700

1

T5

2

T9

3

T12

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	691	1			T1	5		T9	2		T12	2
valid[1]	639	1			T1	4		T3	1		T9	5
valid[2]	671	1			T1	6		T3	1		T5	1
valid[3]	657	1			T1	6		T3	3		T5	1
valid[4]	705	1			T1	4		T3	2		T5	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	102	1			T12	1		T18	3		T34	1
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T1	2		T19	1		T16	2
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T9	3		T12	3		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	164	1			T1	3		T3	1		T16	3
auto[0]	auto[0]	valid[2]	auto[0]	83	1			T12	1		T17	1		T27	1
auto[0]	auto[0]	valid[2]	auto[1]	160	1			T1	4		T16	2		T80	2
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T12	1		T15	1		T18	3
auto[0]	auto[0]	valid[3]	auto[1]	158	1			T1	1		T3	1		T9	1
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T27	2		T34	1		T78	3
auto[0]	auto[0]	valid[4]	auto[1]	173	1			T1	3		T3	1		T9	1
auto[0]	auto[1]	valid[0]	auto[0]	99	1			T9	1		T12	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	186	1			T1	3		T9	1		T16	1
auto[0]	auto[1]	valid[1]	auto[0]	97	1			T9	1		T12	1		T18	2
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T1	1		T16	1		T79	3
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T9	1		T12	1		T17	2
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T1	2		T3	1		T16	1
auto[0]	auto[1]	valid[3]	auto[0]	95	1			T9	2		T15	2		T17	2
auto[0]	auto[1]	valid[3]	auto[1]	178	1			T1	5		T3	2		T5	1
auto[0]	auto[1]	valid[4]	auto[0]	94	1			T12	1		T18	2		T34	2
auto[0]	auto[1]	valid[4]	auto[1]	167	1			T1	1		T3	1		T16	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T27	2		T29	1		T20	3
auto[1]	auto[0]	valid[1]	auto[0]	57	1			T9	1		T12	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	73	1			T5	1		T31	1		T20	3
auto[1]	auto[0]	valid[3]	auto[0]	63	1			T12	1		T31	2		T183	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T5	1		T9	1		T27	3
auto[1]	auto[1]	valid[0]	auto[0]	78	1			T15	1		T34	1		T20	2
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T18	1		T78	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	62	1			T17	1		T27	1		T78	1
auto[1]	auto[1]	valid[3]	auto[0]	62	1			T12	1		T27	1		T78	1
auto[1]	auto[1]	valid[4]	auto[0]	81	1			T9	1		T18	1		T34	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal