Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44443

1

T5

87

T9

275

T11

3

auto[1]

16281

1

T1

225

T3

7

T5

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44267

1

T1

225

T3

7

T5

69

auto[1]

16457

1

T5

25

T9

108

T11

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31448	1			T1	128		T3	7		T5	53
others[1]	5161	1			T1	14		T5	5		T9	27
others[2]	5051	1			T1	19		T5	8		T9	30
others[3]	5738	1			T1	22		T5	7		T9	22
interest[1]	3413	1			T1	5		T5	6		T9	15
interest[4]	20480	1			T1	85		T3	7		T5	39
interest[64]	9913	1			T1	37		T5	15		T9	50

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14461	1			T5	31		T9	88		T12	98
auto[0]	auto[0]	others[1]	2380	1			T5	4		T9	14		T12	24
auto[0]	auto[0]	others[2]	2335	1			T5	7		T9	17		T12	13
auto[0]	auto[0]	others[3]	2654	1			T5	6		T9	12		T12	22
auto[0]	auto[0]	interest[1]	1578	1			T5	3		T9	8		T11	1
auto[0]	auto[0]	interest[4]	9334	1			T5	22		T9	57		T12	54
auto[0]	auto[0]	interest[64]	4578	1			T5	11		T9	28		T12	32
auto[0]	auto[1]	others[0]	8564	1			T1	128		T3	7		T5	5
auto[0]	auto[1]	others[1]	1365	1			T1	14		T9	4		T16	11
auto[0]	auto[1]	others[2]	1303	1			T1	19		T9	2		T16	20
auto[0]	auto[1]	others[3]	1499	1			T1	22		T9	2		T16	20
auto[0]	auto[1]	interest[1]	912	1			T1	5		T9	1		T16	13
auto[0]	auto[1]	interest[4]	5619	1			T1	85		T3	7		T5	3
auto[0]	auto[1]	interest[64]	2638	1			T1	37		T5	2		T9	4
auto[1]	auto[0]	others[0]	8423	1			T5	17		T9	56		T11	2
auto[1]	auto[0]	others[1]	1416	1			T5	1		T9	9		T12	7
auto[1]	auto[0]	others[2]	1413	1			T5	1		T9	11		T12	6
auto[1]	auto[0]	others[3]	1585	1			T5	1		T9	8		T12	7
auto[1]	auto[0]	interest[1]	923	1			T5	3		T9	6		T12	7
auto[1]	auto[0]	interest[4]	5527	1			T5	14		T9	37		T12	37
auto[1]	auto[0]	interest[64]	2697	1			T5	2		T9	18		T12	19

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal