Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	868	1			T9	20		T55	17		T56	24
all_values[1]	868	1			T9	20		T55	17		T56	24
all_values[2]	868	1			T9	20		T55	17		T56	24
all_values[3]	868	1			T9	20		T55	17		T56	24
all_values[4]	868	1			T9	20		T55	17		T56	24
all_values[5]	868	1			T9	20		T55	17		T56	24
all_values[6]	868	1			T9	20		T55	17		T56	24
all_values[7]	868	1			T9	20		T55	17		T56	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3892

1

T9

76

T55

74

T56

108

auto[1]

3052

1

T9

84

T55

62

T56

84

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2725

1

T9

60

T55

53

T56

67

auto[1]

4219

1

T9

100

T55

83

T56

125

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3909

1

T9

86

T55

72

T56

103

auto[1]

3035

1

T9

74

T55

64

T56

89

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	198	1			T9	1		T55	3		T56	4
all_values[0]	auto[0]	auto[0]	auto[1]	105	1			T9	1		T55	1		T56	2
all_values[0]	auto[0]	auto[1]	auto[0]	106	1			T56	9		T165	4		T149	5
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T9	3		T55	3		T165	6
all_values[0]	auto[1]	auto[0]	auto[1]	220	1			T9	6		T55	6		T56	5
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T9	9		T55	4		T56	4
all_values[1]	auto[0]	auto[0]	auto[0]	185	1			T9	6		T55	2		T56	3
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T9	3		T56	3		T165	7
all_values[1]	auto[0]	auto[1]	auto[0]	157	1			T9	5		T55	2		T56	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T9	2		T55	2		T56	3
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T9	1		T55	6		T56	9
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T9	3		T55	5		T56	3
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T9	2		T56	2		T165	7
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T55	2		T56	5		T165	2
all_values[2]	auto[0]	auto[1]	auto[0]	136	1			T9	2		T55	5		T56	1
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T9	4		T55	2		T56	3
all_values[2]	auto[1]	auto[0]	auto[1]	212	1			T9	4		T55	4		T56	6
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T9	8		T55	4		T56	7
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T9	7		T55	5		T56	7
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T55	1		T56	2		T165	2
all_values[3]	auto[0]	auto[1]	auto[0]	153	1			T9	6		T55	3		T56	3
all_values[3]	auto[0]	auto[1]	auto[1]	96	1			T9	2		T55	1		T56	3
all_values[3]	auto[1]	auto[0]	auto[1]	201	1			T9	3		T55	2		T56	3
all_values[3]	auto[1]	auto[1]	auto[1]	167	1			T9	2		T55	5		T56	6
all_values[4]	auto[0]	auto[0]	auto[0]	196	1			T9	2		T55	4		T56	9
all_values[4]	auto[0]	auto[0]	auto[1]	99	1			T55	2		T56	3		T165	6
all_values[4]	auto[0]	auto[1]	auto[0]	127	1			T9	4		T55	2		T56	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T9	1		T55	1		T56	1
all_values[4]	auto[1]	auto[0]	auto[1]	216	1			T9	5		T55	4		T56	4
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T9	8		T55	4		T56	5
all_values[5]	auto[0]	auto[0]	auto[0]	276	1			T9	9		T55	6		T56	7
all_values[5]	auto[0]	auto[1]	auto[0]	213	1			T9	4		T55	6		T56	4
all_values[5]	auto[1]	auto[0]	auto[1]	211	1			T9	3		T55	4		T56	5
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T9	4		T55	1		T56	8
all_values[6]	auto[0]	auto[0]	auto[0]	190	1			T9	4		T55	9		T56	5
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T9	5		T56	1		T165	4
all_values[6]	auto[0]	auto[1]	auto[0]	123	1			T9	2		T55	1		T56	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T9	2		T55	2		T56	2
all_values[6]	auto[1]	auto[0]	auto[1]	216	1			T9	5		T55	1		T56	9
all_values[6]	auto[1]	auto[1]	auto[1]	174	1			T9	2		T55	4		T56	5
all_values[7]	auto[0]	auto[0]	auto[0]	148	1			T9	2		T55	3		T56	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T9	1		T55	2		T56	6
all_values[7]	auto[0]	auto[1]	auto[0]	149	1			T9	4		T55	2		T56	4
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T9	2		T56	2		T165	5
all_values[7]	auto[1]	auto[0]	auto[1]	236	1			T9	6		T55	7		T56	6
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T9	5		T55	3		T56	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal