Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2560830	1			T2	1		T4	378		T6	1
all_values[1]	2560830	1			T2	1		T4	378		T6	1
all_values[2]	2560830	1			T2	1		T4	378		T6	1
all_values[3]	2560830	1			T2	1		T4	378		T6	1
all_values[4]	2560830	1			T2	1		T4	378		T6	1
all_values[5]	2560830	1			T2	1		T4	378		T6	1
all_values[6]	2560830	1			T2	1		T4	378		T6	1
all_values[7]	2560830	1			T2	1		T4	378		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20293360

1

T2

8

T4

3024

T6

8

auto[1]

193280

1

T58

85

T64

1117

T65

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20464807

1

T2

8

T4

3021

T6

8

auto[1]

21833

1

T4

3

T7

215

T10

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2521709	1			T2	1		T4	378		T6	1
all_values[0]	auto[0]	auto[1]	11287	1			T7	177		T12	35		T15	3
all_values[0]	auto[1]	auto[0]	27211	1			T58	5		T64	6		T65	3
all_values[0]	auto[1]	auto[1]	623	1			T58	4		T64	5		T34	217
all_values[1]	auto[0]	auto[0]	2532108	1			T2	1		T4	378		T6	1
all_values[1]	auto[0]	auto[1]	5531	1			T7	30		T12	26		T15	3
all_values[1]	auto[1]	auto[0]	22972	1			T58	6		T64	2		T65	2
all_values[1]	auto[1]	auto[1]	219	1			T58	9		T64	6		T34	4
all_values[2]	auto[0]	auto[0]	2513920	1			T2	1		T4	378		T6	1
all_values[2]	auto[0]	auto[1]	2095	1			T7	8		T12	26		T15	3
all_values[2]	auto[1]	auto[0]	44585	1			T58	4		T64	356		T65	2
all_values[2]	auto[1]	auto[1]	230	1			T58	6		T64	6		T34	32
all_values[3]	auto[0]	auto[0]	2559797	1			T2	1		T4	378		T6	1
all_values[3]	auto[0]	auto[1]	174	1			T58	2		T64	4		T65	1
all_values[3]	auto[1]	auto[0]	686	1			T58	9		T64	4		T65	4
all_values[3]	auto[1]	auto[1]	173	1			T58	2		T64	4		T34	1
all_values[4]	auto[0]	auto[0]	2515416	1			T2	1		T4	378		T6	1
all_values[4]	auto[0]	auto[1]	196	1			T58	5		T64	4		T34	2
all_values[4]	auto[1]	auto[0]	45049	1			T58	9		T64	350		T65	1
all_values[4]	auto[1]	auto[1]	169	1			T58	4		T64	6		T34	7
all_values[5]	auto[0]	auto[0]	2559652	1			T2	1		T4	375		T6	1
all_values[5]	auto[0]	auto[1]	324	1			T4	3		T10	1		T17	7
all_values[5]	auto[1]	auto[0]	707	1			T58	4		T64	7		T34	1
all_values[5]	auto[1]	auto[1]	147	1			T58	3		T64	2		T34	3
all_values[6]	auto[0]	auto[0]	2533672	1			T2	1		T4	378		T6	1
all_values[6]	auto[0]	auto[1]	181	1			T58	1		T64	4		T65	2
all_values[6]	auto[1]	auto[0]	26828	1			T58	4		T64	5		T65	1
all_values[6]	auto[1]	auto[1]	149	1			T58	5		T64	3		T34	3
all_values[7]	auto[0]	auto[0]	2537139	1			T2	1		T4	378		T6	1
all_values[7]	auto[0]	auto[1]	159	1			T58	1		T64	3		T34	1
all_values[7]	auto[1]	auto[0]	23356	1			T58	7		T64	351		T65	2
all_values[7]	auto[1]	auto[1]	176	1			T58	4		T64	4		T65	3