Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29737	1			T6	4		T7	180		T8	6
auto[SpiFlashAddrCfg]	6209	1			T7	55		T8	4		T12	24
auto[SpiFlashAddr3b]	7581	1			T7	44		T8	4		T12	23
auto[SpiFlashAddr4b]	6416	1			T7	38		T8	7		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28688

1

T6

4

T7

164

T8

12

auto[1]

21255

1

T7

153

T8

9

T12

64

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26617

1

T6

4

T7

178

T8

15

auto[1]

23326

1

T7

139

T8

6

T9

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	33643	1			T6	4		T7	218		T8	7
values[1]	932	1			T7	11		T12	2		T13	4
values[2]	1131	1			T7	3		T12	2		T13	2
values[3]	1238	1			T7	8		T8	5		T12	8
values[4]	1196	1			T7	7		T8	2		T12	3
values[5]	1129	1			T7	5		T8	1		T12	10
values[6]	1226	1			T7	3		T12	4		T13	5
values[7]	1211	1			T7	4		T8	1		T9	2
values[8]	8237	1			T7	58		T8	5		T12	42

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24088

1

T6

4

T8

21

T9

14

auto[1]

25855

1

T7

317

T13

176

T41

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48209

1

T6

4

T7

303

T8

21

write

1734

1

T7

14

T12

11

T13

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16601

1

T6

4

T7

109

T8

10

valids[0x1]

33342

1

T7

208

T8

11

T9

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1331	1			T7	6		T9	4		T12	6
internal_process_ops[0x5a]	1363	1			T7	10		T8	1		T12	1
internal_process_ops[0x05]	18220	1			T7	94		T8	1		T9	4
internal_process_ops[0x35]	1317	1			T7	12		T9	4		T12	4
internal_process_ops[0x15]	1285	1			T7	10		T8	3		T12	6
internal_process_ops[0x03]	826	1			T7	4		T12	4		T13	2
internal_process_ops[0x0b]	859	1			T7	5		T8	1		T12	9
internal_process_ops[0x3b]	847	1			T7	2		T8	1		T12	7
internal_process_ops[0x6b]	897	1			T7	5		T12	6		T13	3
internal_process_ops[0xbb]	927	1			T7	2		T9	2		T12	7
internal_process_ops[0xeb]	862	1			T7	3		T12	8		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49131

1

T6

4

T7

308

T8

21

auto[1]

812

1

T7

9

T12

3

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48137

1

T6

4

T7

300

T8

20

auto[1]

1806

1

T7

17

T8

1

T12

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8094

1

T6

4

T8

6

T9

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5103

1

T12

26

T15

184

T92

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1630

1

T8

2

T12

10

T15

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1367

1

T8

2

T12

11

T15

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1999

1

T8

3

T12

13

T15

22

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1815

1

T8

1

T12

10

T15

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1697

1

T8

1

T9

2

T12

26

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1551

1

T8

6

T12

14

T15

29

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

54

1

T12

2

T29

1

T28

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

43

1

T12

3

T15

1

T27

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T12

2

T15

3

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

46

1

T15

1

T64

2

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

55

1

T12

3

T32

1

T18

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

45

1

T15

2

T34

4

T35

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

39

1

T36

1

T166

3

T167

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

47

1

T27

2

T18

2

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

50

1

T15

1

T25

2

T27

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

47

1

T15

1

T29

2

T28

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

40

1

T15

3

T29

1

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

67

1

T15

2

T27

1

T80

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

85

1

T26

2

T28

2

T168

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

56

1

T15

4

T31

2

T32

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

52

1

T12

1

T31

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

52

1

T64

1

T28

1

T32

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9875

1

T7

91

T13

58

T42

56

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6234

1

T7

86

T13

42

T42

44

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1423

1

T7

30

T13

16

T41

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1360

1

T7

22

T13

17

T42

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1713

1

T7

24

T13

11

T41

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1627

1

T7

15

T13

12

T42

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1376

1

T7

17

T13

6

T42

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1345

1

T7

18

T13

7

T42

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

69

1

T42

2

T133

1

T34

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

46

1

T13

1

T79

1

T133

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

49

1

T7

1

T77

3

T79

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T7

2

T13

5

T44

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

53

1

T7

1

T44

1

T79

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

62

1

T42

1

T77

2

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T7

1

T77

6

T79

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

47

1

T7

1

T42

1

T169

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T7

1

T13

1

T170

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

44

1

T44

1

T79

2

T18

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

59

1

T7

1

T42

1

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

52

1

T7

3

T18

1

T163

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

65

1

T42

1

T44

2

T171

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

39

1

T42

2

T77

2

T55

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T42

2

T77

2

T169

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

49

1

T7

3

T42

1

T79

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3122	1			T6	4		T8	3		T12	22
auto[0]	values[0]	valids[0x1]	12252	1			T8	4		T9	12		T12	66
auto[0]	values[1]	valids[0x1]	467	1			T12	2		T15	9		T26	2
auto[0]	values[2]	valids[0x0]	381	1			T12	2		T15	3		T118	2
auto[0]	values[2]	valids[0x1]	208	1			T15	1		T26	2		T31	2
auto[0]	values[3]	valids[0x0]	429	1			T8	5		T12	4		T15	2
auto[0]	values[3]	valids[0x1]	251	1			T12	4		T15	7		T31	2
auto[0]	values[4]	valids[0x0]	456	1			T12	3		T15	5		T38	4
auto[0]	values[4]	valids[0x1]	176	1			T8	2		T15	2		T172	4
auto[0]	values[5]	valids[0x0]	422	1			T8	1		T12	8		T15	6
auto[0]	values[5]	valids[0x1]	190	1			T12	2		T15	3		T31	1
auto[0]	values[6]	valids[0x0]	416	1			T12	2		T15	2		T31	5
auto[0]	values[6]	valids[0x1]	216	1			T12	2		T15	5		T31	4
auto[0]	values[7]	valids[0x0]	389	1			T8	1		T9	2		T12	2
auto[0]	values[7]	valids[0x1]	242	1			T12	3		T15	2		T31	3
auto[0]	values[8]	valids[0x0]	2830	1			T12	28		T15	29		T26	4
auto[0]	values[8]	valids[0x1]	1641	1			T8	5		T12	14		T15	20
auto[1]	values[0]	valids[0x0]	3893	1			T7	61		T13	25		T42	30
auto[1]	values[0]	valids[0x1]	14376	1			T7	157		T13	93		T41	2
auto[1]	values[1]	valids[0x1]	465	1			T7	11		T13	4		T42	3
auto[1]	values[2]	valids[0x0]	318	1			T7	2		T41	2		T42	2
auto[1]	values[2]	valids[0x1]	224	1			T7	1		T13	2		T42	3
auto[1]	values[3]	valids[0x0]	361	1			T7	3		T13	2		T42	1
auto[1]	values[3]	valids[0x1]	197	1			T7	5		T77	5		T79	1
auto[1]	values[4]	valids[0x0]	335	1			T7	5		T13	2		T42	2
auto[1]	values[4]	valids[0x1]	229	1			T7	2		T13	2		T42	1
auto[1]	values[5]	valids[0x0]	299	1			T7	1		T13	8		T42	7
auto[1]	values[5]	valids[0x1]	218	1			T7	4		T42	5		T77	1
auto[1]	values[6]	valids[0x0]	374	1			T13	5		T42	7		T44	1
auto[1]	values[6]	valids[0x1]	220	1			T7	3		T42	3		T44	7
auto[1]	values[7]	valids[0x0]	347	1			T7	3		T13	3		T42	1
auto[1]	values[7]	valids[0x1]	233	1			T7	1		T13	1		T44	6
auto[1]	values[8]	valids[0x0]	2229	1			T7	34		T13	17		T41	3
auto[1]	values[8]	valids[0x1]	1537	1			T7	24		T13	12		T42	18