Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2872155

1

T6

514

T7

17962

T8

2345

auto[1]

16867

1

T7

77

T8

1

T12

24

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

933456

1

T6

514

T7

88

T8

8

auto[1]

1955566

1

T7

17951

T8

2338

T9

1044

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	585566	1			T6	75		T7	1197		T9	118
auto[524288:1048575]	290830	1			T6	3		T7	2734		T9	9
auto[1048576:1572863]	318844	1			T9	302		T12	125		T13	274
auto[1572864:2097151]	317726	1			T6	275		T7	1806		T8	264
auto[2097152:2621439]	382126	1			T6	1		T7	4017		T9	42
auto[2621440:3145727]	346718	1			T6	78		T7	2204		T8	2082
auto[3145728:3670015]	309254	1			T7	5435		T13	956		T15	7
auto[3670016:4194303]	337958	1			T6	82		T7	646		T9	579

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1975521

1

T6

280

T7

18038

T8

2346

auto[1]

913501

1

T6

234

T7

1

T9

262

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2531408

1

T6

514

T7

10731

T8

2082

auto[1]

357614

1

T7

7308

T8

264

T12

1289

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	253229	1			T6	75		T7	10		T9	108
auto[0]	auto[0]	auto[0:524287]	auto[1]	294969	1			T7	1033		T9	10		T12	514
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	80569	1			T6	3		T7	2		T9	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	176316	1			T7	130		T9	8		T42	520
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	77041	1			T9	27		T12	4		T13	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	184418	1			T9	275		T12	120		T13	258
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	104694	1			T6	275		T7	7		T9	77
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	171902	1			T7	348		T9	237		T12	3031
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	106925	1			T6	1		T7	7		T9	32
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	210941	1			T7	3488		T9	10		T12	3074
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	120754	1			T6	78		T7	17		T8	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	189793	1			T7	2183		T8	2077		T12	259
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	82626	1			T7	2		T13	5		T15	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	180376	1			T7	2817		T13	938		T15	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	100050	1			T6	82		T7	3		T9	75
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	182963	1			T7	643		T9	504		T12	768
auto[0]	auto[1]	auto[0:524287]	auto[0]	970	1			T15	1		T27	8		T29	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	33250	1			T7	154		T27	643		T29	2733
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	515	1			T7	9		T42	1		T44	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	31677	1			T7	2570		T42	256		T64	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	712	1			T15	1		T31	1		T77	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54291	1			T31	128		T77	2469		T28	2964
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	231	1			T7	1		T8	3		T12	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	38615	1			T7	1419		T8	261		T15	642
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	899	1			T7	3		T15	1		T27	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61358	1			T7	513		T12	256		T27	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	898	1			T7	2		T12	2		T15	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	33678	1			T7	1		T12	513		T15	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	374	1			T7	8		T13	1		T31	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44126	1			T7	2592		T42	56		T29	384
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1161	1			T12	3		T15	2		T31	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	51834	1			T12	512		T15	3916		T31	12
auto[1]	auto[0]	auto[0:524287]	auto[0]	262	1			T12	2		T13	1		T15	8
auto[1]	auto[0]	auto[0:524287]	auto[1]	2402	1			T12	6		T13	14		T15	115
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	178	1			T7	2		T42	1		T29	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1449	1			T7	7		T42	3		T77	137
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	195	1			T12	1		T13	2		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1645	1			T13	7		T15	34		T27	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	183	1			T7	3		T12	1		T15	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1593	1			T7	22		T12	2		T15	26
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	176	1			T7	1		T12	2		T13	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1415	1			T7	4		T12	8		T13	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	163	1			T8	1		T13	1		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1202	1			T13	6		T15	13		T42	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	154	1			T7	1		T13	2		T15	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1288	1			T7	1		T13	10		T15	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	153	1			T42	2		T27	2		T28	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1384	1			T42	7		T27	14		T28	14
auto[1]	auto[1]	auto[0:524287]	auto[0]	52	1			T27	3		T29	1		T79	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	432	1			T27	50		T29	1		T79	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	24	1			T7	3		T18	1		T35	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	102	1			T7	11		T35	5		T212	15
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	52	1			T77	1		T18	7		T152	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	490	1			T77	5		T18	3		T152	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	47	1			T7	1		T15	1		T28	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	461	1			T7	5		T15	14		T28	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	47	1			T7	1		T29	1		T77	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	365	1			T77	62		T79	2		T80	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	41	1			T7	1		T12	1		T32	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	189	1			T12	1		T32	2		T34	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	46	1			T7	4		T77	1		T198	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	264	1			T7	10		T77	29		T198	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	35	1			T31	3		T77	4		T28	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	378	1			T31	19		T77	66		T28	45

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1607988	1			T6	280		T7	10690		T8	2081
auto[0]	auto[0]	auto[1]	909578	1			T6	234		T9	262		T13	3
auto[0]	auto[1]	auto[0]	351011	1			T7	7272		T8	264		T12	1287
auto[0]	auto[1]	auto[1]	3578	1			T31	3		T74	3		T77	5
auto[1]	auto[0]	auto[0]	13560	1			T7	40		T8	1		T12	20
auto[1]	auto[0]	auto[1]	282	1			T7	1		T12	2		T13	3
auto[1]	auto[1]	auto[0]	2962	1			T7	36		T12	2		T15	15
auto[1]	auto[1]	auto[1]	63	1			T31	1		T27	2		T18	1