Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13855

1

T6

4

T8

12

T9

14

auto[1]

10233

1

T8

9

T12

64

T15

264

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3277	1			T6	4		T15	188		T92	10
values[1]	3069	1			T27	89		T29	43		T78	6
values[2]	2721	1			T9	14		T12	20		T30	14
values[3]	3552	1			T12	51		T15	23		T38	10
values[4]	3434	1			T12	24		T15	133		T172	10
values[5]	2208	1			T12	49		T15	20		T31	69
values[6]	2481	1			T15	140		T31	20		T27	86
values[7]	3346	1			T8	21		T12	20		T25	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2756	1			T6	4		T12	24		T15	131
values[1]	3052	1			T15	76		T172	10		T31	69
values[2]	3448	1			T12	27		T15	87		T31	20
values[3]	2936	1			T8	21		T38	10		T31	20
values[4]	3292	1			T12	44		T15	78		T27	40
values[5]	2355	1			T12	25		T15	92		T208	2
values[6]	2779	1			T9	14		T12	44		T15	20
values[7]	3470	1			T15	20		T26	18		T25	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	109	1			T6	4		T27	12		T184	19
auto[0]	values[0]	values[1]	222	1			T15	67		T29	15		T167	15
auto[0]	values[0]	values[2]	258	1			T45	18		T194	15		T237	4
auto[0]	values[0]	values[3]	292	1			T167	12		T45	16		T238	30
auto[0]	values[0]	values[4]	246	1			T27	9		T29	8		T32	13
auto[0]	values[0]	values[5]	259	1			T15	69		T34	10		T189	8
auto[0]	values[0]	values[6]	261	1			T32	10		T80	10		T239	62
auto[0]	values[0]	values[7]	405	1			T15	6		T29	25		T28	8
auto[0]	values[1]	values[0]	196	1			T29	11		T34	10		T166	16
auto[0]	values[1]	values[1]	379	1			T18	12		T152	8		T47	12
auto[0]	values[1]	values[2]	347	1			T27	15		T78	6		T28	64
auto[0]	values[1]	values[3]	105	1			T80	9		T225	2		T158	32
auto[0]	values[1]	values[4]	192	1			T27	10		T37	14		T198	25
auto[0]	values[1]	values[5]	156	1			T165	13		T45	44		T240	17
auto[0]	values[1]	values[6]	133	1			T27	12		T181	16		T184	14
auto[0]	values[1]	values[7]	370	1			T27	10		T29	16		T32	36
auto[0]	values[2]	values[0]	114	1			T30	14		T231	6		T241	8
auto[0]	values[2]	values[1]	257	1			T31	5		T28	14		T18	8
auto[0]	values[2]	values[2]	222	1			T27	34		T168	11		T242	6
auto[0]	values[2]	values[3]	137	1			T29	15		T80	7		T191	11
auto[0]	values[2]	values[4]	285	1			T12	10		T80	23		T198	33
auto[0]	values[2]	values[5]	145	1			T191	13		T243	16		T195	15
auto[0]	values[2]	values[6]	210	1			T9	14		T31	11		T18	23
auto[0]	values[2]	values[7]	149	1			T26	18		T80	6		T184	12
auto[0]	values[3]	values[0]	463	1			T12	13		T15	15		T27	13
auto[0]	values[3]	values[1]	336	1			T80	57		T244	54		T201	8
auto[0]	values[3]	values[2]	147	1			T12	12		T243	8		T245	61
auto[0]	values[3]	values[3]	149	1			T38	10		T29	11		T32	8
auto[0]	values[3]	values[4]	289	1			T64	12		T34	14		T246	12
auto[0]	values[3]	values[5]	281	1			T208	2		T247	2		T217	13
auto[0]	values[3]	values[6]	198	1			T32	9		T34	8		T198	26
auto[0]	values[3]	values[7]	233	1			T248	6		T37	12		T80	12
auto[0]	values[4]	values[0]	150	1			T15	8		T29	14		T32	10
auto[0]	values[4]	values[1]	260	1			T172	10		T27	13		T36	12
auto[0]	values[4]	values[2]	207	1			T249	16		T192	8		T53	6
auto[0]	values[4]	values[3]	287	1			T166	12		T167	13		T250	6
auto[0]	values[4]	values[4]	331	1			T12	19		T15	9		T217	11
auto[0]	values[4]	values[5]	88	1			T198	9		T251	4		T45	7
auto[0]	values[4]	values[6]	120	1			T152	11		T252	8		T240	9
auto[0]	values[4]	values[7]	288	1			T31	13		T27	10		T28	10
auto[0]	values[5]	values[0]	101	1			T52	14		T158	8		T253	6
auto[0]	values[5]	values[1]	237	1			T31	37		T28	13		T200	10
auto[0]	values[5]	values[2]	85	1			T88	16		T240	15		T194	13
auto[0]	values[5]	values[3]	162	1			T28	12		T18	19		T254	6
auto[0]	values[5]	values[4]	158	1			T64	10		T34	20		T200	13
auto[0]	values[5]	values[5]	176	1			T12	17		T198	57		T255	2
auto[0]	values[5]	values[6]	220	1			T12	14		T15	14		T256	2
auto[0]	values[5]	values[7]	81	1			T31	15		T168	15		T80	10
auto[0]	values[6]	values[0]	220	1			T15	44		T37	9		T166	11
auto[0]	values[6]	values[1]	137	1			T72	26		T257	10		T182	13
auto[0]	values[6]	values[2]	276	1			T15	8		T27	35		T36	34
auto[0]	values[6]	values[3]	209	1			T31	11		T27	7		T166	16
auto[0]	values[6]	values[4]	119	1			T37	16		T258	10		T152	22
auto[0]	values[6]	values[5]	231	1			T87	6		T215	17		T259	2
auto[0]	values[6]	values[6]	107	1			T86	10		T260	12		T261	8
auto[0]	values[6]	values[7]	100	1			T187	11		T220	12		T262	13
auto[0]	values[7]	values[0]	217	1			T27	13		T37	11		T167	28
auto[0]	values[7]	values[1]	150	1			T74	10		T36	13		T263	12
auto[0]	values[7]	values[2]	317	1			T31	13		T27	13		T75	8
auto[0]	values[7]	values[3]	338	1			T8	12		T162	10		T18	14
auto[0]	values[7]	values[4]	240	1			T64	9		T28	12		T198	20
auto[0]	values[7]	values[5]	154	1			T32	13		T164	11		T215	12
auto[0]	values[7]	values[6]	288	1			T12	15		T31	7		T264	6
auto[0]	values[7]	values[7]	256	1			T25	6		T91	20		T29	11
auto[1]	values[0]	values[0]	75	1			T92	10		T27	8		T184	6
auto[1]	values[0]	values[1]	196	1			T15	9		T29	6		T167	10
auto[1]	values[0]	values[2]	169	1			T45	7		T194	5		T158	11
auto[1]	values[0]	values[3]	161	1			T161	26		T167	8		T45	8
auto[1]	values[0]	values[4]	176	1			T27	11		T29	13		T32	7
auto[1]	values[0]	values[5]	77	1			T15	23		T34	10		T80	11
auto[1]	values[0]	values[6]	223	1			T32	10		T80	44		T191	5
auto[1]	values[0]	values[7]	148	1			T15	14		T29	11		T28	14
auto[1]	values[1]	values[0]	205	1			T29	10		T34	17		T166	4
auto[1]	values[1]	values[1]	113	1			T18	9		T152	21		T47	11
auto[1]	values[1]	values[2]	270	1			T27	5		T28	6		T32	8
auto[1]	values[1]	values[3]	51	1			T80	12		T158	12		T209	10
auto[1]	values[1]	values[4]	121	1			T27	10		T37	6		T198	20
auto[1]	values[1]	values[5]	53	1			T165	7		T45	11		T240	3
auto[1]	values[1]	values[6]	154	1			T27	17		T184	11		T265	2
auto[1]	values[1]	values[7]	224	1			T27	10		T29	6		T32	39
auto[1]	values[2]	values[0]	64	1			T45	16		T266	13		T220	7
auto[1]	values[2]	values[1]	134	1			T31	15		T28	6		T18	17
auto[1]	values[2]	values[2]	193	1			T27	11		T168	17		T37	10
auto[1]	values[2]	values[3]	187	1			T29	6		T80	112		T267	6
auto[1]	values[2]	values[4]	169	1			T12	10		T80	4		T198	16
auto[1]	values[2]	values[5]	152	1			T191	7		T243	4		T195	5
auto[1]	values[2]	values[6]	214	1			T31	9		T18	19		T34	16
auto[1]	values[2]	values[7]	89	1			T80	57		T184	8		T207	11
auto[1]	values[3]	values[0]	277	1			T12	11		T15	8		T27	7
auto[1]	values[3]	values[1]	159	1			T80	7		T191	10		T268	12
auto[1]	values[3]	values[2]	112	1			T12	15		T243	14		T269	5
auto[1]	values[3]	values[3]	213	1			T29	9		T32	16		T168	8
auto[1]	values[3]	values[4]	246	1			T64	8		T34	8		T246	84
auto[1]	values[3]	values[5]	129	1			T270	10		T217	7		T219	25
auto[1]	values[3]	values[6]	181	1			T32	12		T34	12		T198	14
auto[1]	values[3]	values[7]	139	1			T37	8		T80	12		T187	8
auto[1]	values[4]	values[0]	161	1			T15	47		T29	18		T32	15
auto[1]	values[4]	values[1]	166	1			T27	7		T36	9		T166	11
auto[1]	values[4]	values[2]	179	1			T37	8		T200	9		T182	5
auto[1]	values[4]	values[3]	136	1			T166	9		T167	9		T154	7
auto[1]	values[4]	values[4]	378	1			T12	5		T15	69		T217	40
auto[1]	values[4]	values[5]	50	1			T198	11		T45	13		T182	9
auto[1]	values[4]	values[6]	142	1			T152	9		T240	15		T216	12
auto[1]	values[4]	values[7]	491	1			T31	7		T27	44		T28	43
auto[1]	values[5]	values[0]	117	1			T158	19		T253	22		T271	10
auto[1]	values[5]	values[1]	103	1			T31	12		T28	7		T200	10
auto[1]	values[5]	values[2]	100	1			T118	14		T240	9		T194	8
auto[1]	values[5]	values[3]	151	1			T28	32		T18	7		T167	5
auto[1]	values[5]	values[4]	75	1			T64	10		T34	3		T200	7
auto[1]	values[5]	values[5]	200	1			T12	8		T198	4		T166	11
auto[1]	values[5]	values[6]	138	1			T12	10		T15	6		T167	17
auto[1]	values[5]	values[7]	104	1			T31	5		T168	5		T80	29
auto[1]	values[6]	values[0]	111	1			T15	9		T37	11		T166	10
auto[1]	values[6]	values[1]	99	1			T182	27		T272	11		T271	23
auto[1]	values[6]	values[2]	327	1			T15	79		T27	11		T36	19
auto[1]	values[6]	values[3]	194	1			T31	9		T27	33		T166	7
auto[1]	values[6]	values[4]	68	1			T37	4		T152	26		T202	24
auto[1]	values[6]	values[5]	65	1			T215	23		T238	11		T273	4
auto[1]	values[6]	values[6]	71	1			T243	19		T266	11		T220	5
auto[1]	values[6]	values[7]	147	1			T187	9		T220	10		T262	18
auto[1]	values[7]	values[0]	176	1			T27	7		T37	9		T167	6
auto[1]	values[7]	values[1]	104	1			T36	7		T166	21		T203	7
auto[1]	values[7]	values[2]	239	1			T31	7		T27	7		T28	41
auto[1]	values[7]	values[3]	164	1			T8	9		T18	8		T33	16
auto[1]	values[7]	values[4]	199	1			T64	53		T28	8		T198	9
auto[1]	values[7]	values[5]	139	1			T32	11		T164	9		T215	10
auto[1]	values[7]	values[6]	119	1			T12	5		T31	13		T200	10
auto[1]	values[7]	values[7]	246	1			T29	9		T80	7		T198	8