Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	312	1			T9	2		T12	4		T15	1
auto[ReadAddrCrossIntoMailbox]	257	1			T12	2		T15	3		T172	2
auto[ReadAddrCrossOutOfMailbox]	243	1			T12	3		T15	3		T31	4
auto[ReadAddrCrossAllMailbox]	139	1			T12	3		T15	1		T172	6
auto[ReadAddrOutsideMailbox]	2798	1			T8	2		T12	29		T15	25

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1847

1

T8

1

T9

1

T12

24

auto[1]

1902

1

T8

1

T9

1

T12

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	588	1			T12	4		T15	4		T208	2
read_ops[0x0b]	630	1			T8	1		T12	9		T15	2
read_ops[0x3b]	610	1			T8	1		T12	7		T15	10
read_ops[0x6b]	662	1			T12	6		T15	5		T31	7
read_ops[0xbb]	649	1			T9	2		T12	7		T15	7
read_ops[0xeb]	610	1			T12	8		T15	5		T31	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T80	1		T45	1		T204	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T32	1		T37	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	9	1			T172	1		T37	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T15	1		T172	1		T31	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T28	1		T137	1		T18	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T137	1		T198	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T172	1		T45	1		T202	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T15	1		T172	1		T31	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	217	1			T12	3		T15	1		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T12	1		T15	1		T208	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T12	1		T38	1		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T38	1		T29	1		T28	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T34	1		T167	1		T216	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T28	1		T168	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T31	1		T27	2		T29	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T191	2		T202	1		T195	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T198	1		T209	1		T238	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T168	1		T167	1		T19	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	241	1			T12	7		T31	2		T27	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T8	1		T12	1		T15	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T12	1		T137	1		T80	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T12	1		T27	1		T137	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T31	1		T32	1		T168	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T12	1		T15	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T31	1		T27	2		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T27	1		T36	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T29	1		T137	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T31	2		T27	2		T137	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	199	1			T8	1		T12	1		T15	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T12	3		T15	5		T26	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T28	1		T137	1		T164	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T15	1		T137	1		T168	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T12	1		T27	5		T18	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T27	1		T29	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T27	4		T37	2		T80	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T12	1		T15	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T12	1		T274	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T28	1		T215	1		T165	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T12	1		T15	1		T31	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T12	2		T15	2		T31	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T9	1		T12	1		T38	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T9	1		T38	2		T172	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T28	2		T137	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T31	1		T137	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T15	2		T18	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T12	1		T27	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T172	2		T34	1		T89	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T12	1		T172	2		T28	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	247	1			T12	1		T15	4		T26	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	227	1			T12	3		T15	1		T26	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T31	1		T80	2		T224	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T28	1		T37	2		T80	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T29	1		T32	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T15	1		T18	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T31	1		T18	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T12	1		T28	3		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T12	1		T28	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T184	1		T209	1		T235	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	230	1			T12	5		T15	1		T31	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T12	1		T15	3		T31	3