Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2560830	1			T2	1		T4	378		T6	1
all_pins[1]	2560830	1			T2	1		T4	378		T6	1
all_pins[2]	2560830	1			T2	1		T4	378		T6	1
all_pins[3]	2560830	1			T2	1		T4	378		T6	1
all_pins[4]	2560830	1			T2	1		T4	378		T6	1
all_pins[5]	2560830	1			T2	1		T4	378		T6	1
all_pins[6]	2560830	1			T2	1		T4	378		T6	1
all_pins[7]	2560830	1			T2	1		T4	378		T6	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20459008	1			T2	8		T4	3024		T6	8
values[0x1]	27632	1			T58	37		T64	36		T65	3
transitions[0x0=>0x1]	27148	1			T58	24		T64	23		T65	3
transitions[0x1=>0x0]	27162	1			T58	24		T64	23		T65	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2560164	1			T2	1		T4	378		T6	1
all_pins[0]	values[0x1]	666	1			T58	4		T64	5		T34	232
all_pins[0]	transitions[0x0=>0x1]	557	1			T58	2		T64	2		T34	232
all_pins[0]	transitions[0x1=>0x0]	117	1			T58	7		T64	3		T34	4
all_pins[1]	values[0x0]	2560604	1			T2	1		T4	378		T6	1
all_pins[1]	values[0x1]	226	1			T58	9		T64	6		T34	4
all_pins[1]	transitions[0x0=>0x1]	166	1			T58	5		T64	3		T34	4
all_pins[1]	transitions[0x1=>0x0]	175	1			T58	2		T64	3		T34	34
all_pins[2]	values[0x0]	2560595	1			T2	1		T4	378		T6	1
all_pins[2]	values[0x1]	235	1			T58	6		T64	6		T34	34
all_pins[2]	transitions[0x0=>0x1]	179	1			T58	4		T64	3		T34	34
all_pins[2]	transitions[0x1=>0x0]	117	1			T64	1		T34	1		T164	1
all_pins[3]	values[0x0]	2560657	1			T2	1		T4	378		T6	1
all_pins[3]	values[0x1]	173	1			T58	2		T64	4		T34	1
all_pins[3]	transitions[0x0=>0x1]	137	1			T64	2		T34	1		T164	3
all_pins[3]	transitions[0x1=>0x0]	133	1			T58	2		T64	4		T34	7
all_pins[4]	values[0x0]	2560661	1			T2	1		T4	378		T6	1
all_pins[4]	values[0x1]	169	1			T58	4		T64	6		T34	7
all_pins[4]	transitions[0x0=>0x1]	131	1			T58	3		T64	6		T34	6
all_pins[4]	transitions[0x1=>0x0]	166	1			T58	2		T64	2		T34	2
all_pins[5]	values[0x0]	2560626	1			T2	1		T4	378		T6	1
all_pins[5]	values[0x1]	204	1			T58	3		T64	2		T34	3
all_pins[5]	transitions[0x0=>0x1]	120	1			T58	3		T64	2		T34	3
all_pins[5]	transitions[0x1=>0x0]	25699	1			T58	5		T64	3		T34	5081
all_pins[6]	values[0x0]	2535047	1			T2	1		T4	378		T6	1
all_pins[6]	values[0x1]	25783	1			T58	5		T64	3		T34	5081
all_pins[6]	transitions[0x0=>0x1]	25739	1			T58	4		T64	2		T34	5080
all_pins[6]	transitions[0x1=>0x0]	132	1			T58	3		T64	3		T65	3
all_pins[7]	values[0x0]	2560654	1			T2	1		T4	378		T6	1
all_pins[7]	values[0x1]	176	1			T58	4		T64	4		T65	3
all_pins[7]	transitions[0x0=>0x1]	119	1			T58	3		T64	3		T65	3
all_pins[7]	transitions[0x1=>0x0]	623	1			T58	3		T64	4		T34	231