Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2739	1			T15	75		T27	60		T78	6
values[1]	3225	1			T8	21		T12	51		T15	53
values[2]	3890	1			T30	14		T38	10		T208	2
values[3]	2345	1			T12	24		T15	20		T27	40
values[4]	3029	1			T6	4		T9	14		T12	40
values[5]	3034	1			T12	24		T15	40		T92	10
values[6]	3124	1			T15	206		T31	40		T29	36
values[7]	2702	1			T12	25		T15	110		T26	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3233	1			T12	51		T38	10		T91	20
values[1]	2986	1			T12	24		T15	53		T172	10
values[2]	2913	1			T15	87		T31	49		T27	20
values[3]	2687	1			T8	21		T15	128		T26	18
values[4]	3154	1			T12	20		T15	63		T31	20
values[5]	2709	1			T9	14		T12	25		T15	98
values[6]	2738	1			T15	55		T29	20		T64	62
values[7]	3668	1			T6	4		T12	44		T15	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23685

1

T6

4

T8

21

T9

14

auto[1]

403

1

T12

3

T15

11

T31

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	465	1			T27	20		T18	19		T275	16
auto[0]	values[0]	values[1]	530	1			T78	6		T181	16		T218	22
auto[0]	values[0]	values[2]	281	1			T27	20		T168	20		T167	32
auto[0]	values[0]	values[3]	241	1			T27	20		T231	6		T37	20
auto[0]	values[0]	values[4]	327	1			T15	20		T32	18		T37	20
auto[0]	values[0]	values[5]	245	1			T32	25		T198	19		T167	19
auto[0]	values[0]	values[6]	350	1			T15	54		T167	20		T200	20
auto[0]	values[0]	values[7]	252	1			T32	47		T45	20		T191	34
auto[0]	values[1]	values[0]	317	1			T12	27		T18	21		T198	23
auto[0]	values[1]	values[1]	402	1			T12	24		T15	53		T172	10
auto[0]	values[1]	values[2]	317	1			T32	25		T37	31		T80	54
auto[0]	values[1]	values[3]	255	1			T8	21		T36	20		T215	34
auto[0]	values[1]	values[4]	378	1			T31	20		T34	26		T215	20
auto[0]	values[1]	values[5]	663	1			T29	21		T200	20		T276	10
auto[0]	values[1]	values[6]	244	1			T257	10		T19	20		T203	28
auto[0]	values[1]	values[7]	601	1			T244	54		T240	29		T202	25
auto[0]	values[2]	values[0]	566	1			T38	10		T27	20		T32	23
auto[0]	values[2]	values[1]	325	1			T29	21		T198	26		T277	12
auto[0]	values[2]	values[2]	464	1			T251	4		T165	31		T202	20
auto[0]	values[2]	values[3]	615	1			T29	42		T37	20		T278	4
auto[0]	values[2]	values[4]	332	1			T27	46		T80	23		T215	20
auto[0]	values[2]	values[5]	320	1			T30	14		T208	2		T31	20
auto[0]	values[2]	values[6]	449	1			T64	59		T53	6		T87	6
auto[0]	values[2]	values[7]	756	1			T27	20		T28	62		T161	26
auto[0]	values[3]	values[0]	369	1			T165	20		T167	21		T279	10
auto[0]	values[3]	values[1]	405	1			T18	22		T193	8		T167	21
auto[0]	values[3]	values[2]	143	1			T18	22		T246	20		T158	19
auto[0]	values[3]	values[3]	294	1			T80	20		T270	10		T166	23
auto[0]	values[3]	values[4]	272	1			T72	26		T280	94		T201	8
auto[0]	values[3]	values[5]	206	1			T15	16		T27	37		T64	20
auto[0]	values[3]	values[6]	285	1			T29	20		T137	12		T80	36
auto[0]	values[3]	values[7]	333	1			T12	21		T168	25		T35	25
auto[0]	values[4]	values[0]	482	1			T31	20		T27	20		T80	61
auto[0]	values[4]	values[1]	259	1			T256	2		T28	20		T34	32
auto[0]	values[4]	values[2]	389	1			T37	20		T166	28		T281	2
auto[0]	values[4]	values[3]	166	1			T191	20		T203	21		T195	20
auto[0]	values[4]	values[4]	523	1			T12	20		T27	20		T34	26
auto[0]	values[4]	values[5]	282	1			T9	14		T31	20		T29	21
auto[0]	values[4]	values[6]	443	1			T18	23		T166	20		T184	20
auto[0]	values[4]	values[7]	430	1			T6	4		T12	20		T25	6
auto[0]	values[5]	values[0]	472	1			T12	24		T91	20		T27	45
auto[0]	values[5]	values[1]	277	1			T164	24		T185	8		T45	25
auto[0]	values[5]	values[2]	507	1			T31	49		T282	10		T33	12
auto[0]	values[5]	values[3]	228	1			T118	14		T36	26		T80	39
auto[0]	values[5]	values[4]	375	1			T15	20		T28	20		T32	20
auto[0]	values[5]	values[5]	345	1			T92	10		T75	8		T64	20
auto[0]	values[5]	values[6]	431	1			T37	18		T80	27		T283	6
auto[0]	values[5]	values[7]	340	1			T15	20		T29	30		T28	53
auto[0]	values[6]	values[0]	237	1			T32	23		T168	20		T284	4
auto[0]	values[6]	values[1]	459	1			T31	18		T18	22		T36	21
auto[0]	values[6]	values[2]	337	1			T165	20		T152	24		T45	22
auto[0]	values[6]	values[3]	517	1			T15	124		T52	14		T35	20
auto[0]	values[6]	values[4]	430	1			T32	21		T215	22		T239	62
auto[0]	values[6]	values[5]	333	1			T15	77		T29	36		T202	31
auto[0]	values[6]	values[6]	246	1			T35	27		T165	27		T167	20
auto[0]	values[6]	values[7]	504	1			T31	20		T80	54		T167	44
auto[0]	values[7]	values[0]	285	1			T27	20		T28	22		T34	20
auto[0]	values[7]	values[1]	269	1			T27	20		T264	6		T252	8
auto[0]	values[7]	values[2]	421	1			T15	87		T227	14		T19	22
auto[0]	values[7]	values[3]	337	1			T26	18		T28	53		T168	28
auto[0]	values[7]	values[4]	447	1			T15	22		T164	18		T198	49
auto[0]	values[7]	values[5]	275	1			T12	25		T31	20		T74	10
auto[0]	values[7]	values[6]	243	1			T242	6		T285	12		T19	22
auto[0]	values[7]	values[7]	394	1			T29	21		T34	40		T37	20
auto[1]	values[0]	values[0]	7	1			T18	1		T45	1		T217	3
auto[1]	values[0]	values[1]	9	1			T218	4		T158	1		T253	1
auto[1]	values[0]	values[2]	5	1			T167	1		T266	3		T286	1
auto[1]	values[0]	values[3]	1	1			T287	1		-	-		-	-
auto[1]	values[0]	values[4]	6	1			T32	2		T158	2		T206	1
auto[1]	values[0]	values[5]	2	1			T198	1		T167	1		-	-
auto[1]	values[0]	values[6]	8	1			T15	1		T243	3		T238	3
auto[1]	values[0]	values[7]	10	1			T32	2		T191	1		T203	1
auto[1]	values[1]	values[0]	5	1			T184	2		T182	2		T288	1
auto[1]	values[1]	values[1]	3	1			T243	1		T238	2		-	-
auto[1]	values[1]	values[2]	13	1			T32	1		T200	2		T289	8
auto[1]	values[1]	values[3]	2	1			T205	1		T290	1		-	-
auto[1]	values[1]	values[4]	4	1			T34	1		T217	1		T269	2
auto[1]	values[1]	values[5]	7	1			T246	2		T158	3		T291	1
auto[1]	values[1]	values[6]	5	1			T203	1		T205	4		-	-
auto[1]	values[1]	values[7]	9	1			T202	1		T292	6		T288	1
auto[1]	values[2]	values[0]	9	1			T217	1		T209	2		T293	3
auto[1]	values[2]	values[1]	4	1			T240	1		T253	2		T294	1
auto[1]	values[2]	values[2]	5	1			T158	2		T295	2		T293	1
auto[1]	values[2]	values[3]	6	1			T45	1		T219	1		T253	3
auto[1]	values[2]	values[4]	8	1			T80	1		T200	1		T158	3
auto[1]	values[2]	values[5]	6	1			T27	1		T28	1		T32	1
auto[1]	values[2]	values[6]	10	1			T64	3		T165	1		T154	1
auto[1]	values[2]	values[7]	15	1			T28	2		T164	1		T184	1
auto[1]	values[3]	values[0]	3	1			T246	1		T194	1		T271	1
auto[1]	values[3]	values[1]	8	1			T18	3		T167	1		T294	4
auto[1]	values[3]	values[2]	1	1			T158	1		-	-		-	-
auto[1]	values[3]	values[3]	4	1			T165	1		T187	2		T202	1
auto[1]	values[3]	values[4]	4	1			T296	4		-	-		-	-
auto[1]	values[3]	values[5]	9	1			T15	4		T27	3		T297	2
auto[1]	values[3]	values[6]	4	1			T198	1		T216	2		T243	1
auto[1]	values[3]	values[7]	5	1			T12	3		T45	1		T213	1
auto[1]	values[4]	values[0]	6	1			T80	2		T182	1		T206	1
auto[1]	values[4]	values[1]	7	1			T34	4		T19	2		T298	1
auto[1]	values[4]	values[2]	9	1			T202	2		T234	3		T299	1
auto[1]	values[4]	values[3]	3	1			T203	2		T253	1		-	-
auto[1]	values[4]	values[4]	17	1			T34	1		T240	1		T300	4
auto[1]	values[4]	values[5]	4	1			T37	1		T166	1		T267	2
auto[1]	values[4]	values[6]	5	1			T18	3		T301	1		T293	1
auto[1]	values[4]	values[7]	4	1			T27	1		T80	2		T238	1
auto[1]	values[5]	values[0]	3	1			T45	1		T158	1		T290	1
auto[1]	values[5]	values[1]	9	1			T45	4		T302	3		T303	2
auto[1]	values[5]	values[2]	10	1			T33	4		T34	2		T191	2
auto[1]	values[5]	values[3]	2	1			T36	1		T195	1		-	-
auto[1]	values[5]	values[4]	16	1			T166	1		T19	2		T243	1
auto[1]	values[5]	values[5]	6	1			T304	4		T286	1		T305	1
auto[1]	values[5]	values[6]	7	1			T37	2		T187	1		T253	1
auto[1]	values[5]	values[7]	6	1			T29	2		T154	1		T219	1
auto[1]	values[6]	values[0]	5	1			T32	1		T306	1		T234	3
auto[1]	values[6]	values[1]	15	1			T31	2		T198	1		T166	1
auto[1]	values[6]	values[2]	6	1			T45	2		T271	1		T205	1
auto[1]	values[6]	values[3]	12	1			T15	4		T246	3		T240	2
auto[1]	values[6]	values[4]	9	1			T165	1		T184	1		T152	1
auto[1]	values[6]	values[5]	5	1			T15	1		T202	2		T287	2
auto[1]	values[6]	values[6]	6	1			T35	5		T158	1		-	-
auto[1]	values[6]	values[7]	3	1			T167	1		T290	2		-	-
auto[1]	values[7]	values[0]	2	1			T154	1		T203	1		-	-
auto[1]	values[7]	values[1]	5	1			T243	2		T233	1		T205	2
auto[1]	values[7]	values[2]	5	1			T307	1		T232	1		T271	3
auto[1]	values[7]	values[3]	4	1			T49	3		T308	1		-	-
auto[1]	values[7]	values[4]	6	1			T15	1		T164	2		T205	1
auto[1]	values[7]	values[5]	1	1			T199	1		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T158	1		T308	1		-	-
auto[1]	values[7]	values[7]	6	1			T34	2		T195	1		T286	2