Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T2

17

T7

9

T8

1

auto[1]

1893

1

T2

15

T7

6

T11

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1970

1

T7

12

T8

1

T11

25

auto[1]

1815

1

T2

32

T7

3

T12

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3034

1

T2

32

T7

8

T11

16

auto[1]

751

1

T7

7

T8

1

T11

9

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	820	1			T2	6		T7	5		T11	8
valid[1]	710	1			T2	8		T7	3		T8	1
valid[2]	708	1			T2	5		T7	3		T11	2
valid[3]	791	1			T2	9		T7	2		T11	5
valid[4]	756	1			T2	4		T7	2		T11	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	136	1			T7	1		T11	6		T12	1
auto[0]	auto[0]	valid[0]	auto[1]	201	1			T2	2		T7	1		T12	1
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T11	1		T42	2		T29	1
auto[0]	auto[0]	valid[1]	auto[1]	170	1			T2	3		T73	1		T32	1
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T7	1		T43	1		T79	1
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T2	5		T16	1		T29	1
auto[0]	auto[0]	valid[3]	auto[0]	126	1			T11	2		T12	1		T42	3
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T2	3		T7	1		T16	1
auto[0]	auto[0]	valid[4]	auto[0]	107	1			T7	1		T12	1		T42	1
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T2	4		T73	2		T32	1
auto[0]	auto[1]	valid[0]	auto[0]	141	1			T7	1		T11	2		T42	2
auto[0]	auto[1]	valid[0]	auto[1]	182	1			T2	4		T7	1		T16	5
auto[0]	auto[1]	valid[1]	auto[0]	117	1			T7	1		T11	2		T15	1
auto[0]	auto[1]	valid[1]	auto[1]	178	1			T2	5		T29	1		T73	1
auto[0]	auto[1]	valid[2]	auto[0]	102	1			T11	1		T12	2		T42	1
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T16	3		T73	1		T76	2
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T11	1		T12	1		T42	1
auto[0]	auto[1]	valid[3]	auto[1]	201	1			T2	6		T16	1		T29	1
auto[0]	auto[1]	valid[4]	auto[0]	126	1			T11	1		T12	2		T44	1
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T16	1		T29	1		T73	3
auto[1]	auto[0]	valid[0]	auto[0]	85	1			T85	1		T42	1		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T7	2		T8	1		T11	3
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T7	1		T42	1		T44	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T7	1		T11	1		T12	2
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T11	2		T12	2		T29	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T7	1		T12	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T11	1		T12	1		T42	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T7	1		T11	1		T134	2
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T11	1		T12	1		T29	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T7	1		T42	1		T79	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal