Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50405

1

T4

9

T7

420

T8

48

auto[1]

18622

1

T2

353

T7

73

T8

35

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50614

1

T2

353

T4

4

T7

337

auto[1]

18413

1

T4

5

T7

156

T8

27

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35421	1			T2	182		T4	2		T7	240
others[1]	5846	1			T2	36		T7	37		T8	10
others[2]	5837	1			T2	34		T7	40		T8	6
others[3]	6735	1			T2	27		T4	2		T7	48
interest[1]	3848	1			T2	21		T7	38		T8	5
interest[4]	23169	1			T2	97		T4	1		T7	143
interest[64]	11340	1			T2	53		T4	5		T7	90

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16197	1			T4	2		T7	128		T8	13
auto[0]	auto[0]	others[1]	2765	1			T7	25		T11	19		T12	21
auto[0]	auto[0]	others[2]	2779	1			T7	24		T8	1		T11	19
auto[0]	auto[0]	others[3]	3119	1			T7	25		T8	4		T11	29
auto[0]	auto[0]	interest[1]	1804	1			T7	21		T8	1		T10	1
auto[0]	auto[0]	interest[4]	10578	1			T4	1		T7	83		T8	7
auto[0]	auto[0]	interest[64]	5328	1			T4	2		T7	41		T8	2
auto[0]	auto[1]	others[0]	9735	1			T2	182		T7	34		T8	20
auto[0]	auto[1]	others[1]	1503	1			T2	36		T7	3		T8	5
auto[0]	auto[1]	others[2]	1568	1			T2	34		T7	4		T8	2
auto[0]	auto[1]	others[3]	1856	1			T2	27		T7	5		T8	2
auto[0]	auto[1]	interest[1]	993	1			T2	21		T7	9		T8	2
auto[0]	auto[1]	interest[4]	6453	1			T2	97		T7	19		T8	13
auto[0]	auto[1]	interest[64]	2967	1			T2	53		T7	18		T8	4
auto[1]	auto[0]	others[0]	9489	1			T7	78		T8	9		T10	3
auto[1]	auto[0]	others[1]	1578	1			T7	9		T8	5		T10	1
auto[1]	auto[0]	others[2]	1490	1			T7	12		T8	3		T11	15
auto[1]	auto[0]	others[3]	1760	1			T4	2		T7	18		T8	1
auto[1]	auto[0]	interest[1]	1051	1			T7	8		T8	2		T11	13
auto[1]	auto[0]	interest[4]	6138	1			T7	41		T8	7		T10	2
auto[1]	auto[0]	interest[64]	3045	1			T4	3		T7	31		T8	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal