Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[1] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[2] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[3] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[4] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[5] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[6] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
all_values[7] |
706 |
1 |
|
|
T58 |
17 |
|
T64 |
17 |
|
T65 |
4 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2928 |
1 |
|
|
T58 |
69 |
|
T64 |
70 |
|
T65 |
21 |
auto[1] |
2720 |
1 |
|
|
T58 |
67 |
|
T64 |
66 |
|
T65 |
11 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2218 |
1 |
|
|
T58 |
54 |
|
T64 |
51 |
|
T65 |
17 |
auto[1] |
3430 |
1 |
|
|
T58 |
82 |
|
T64 |
85 |
|
T65 |
15 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3236 |
1 |
|
|
T58 |
77 |
|
T64 |
75 |
|
T65 |
21 |
auto[1] |
2412 |
1 |
|
|
T58 |
59 |
|
T64 |
61 |
|
T65 |
11 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
48 |
2 |
46 |
95.83 |
2 |
Automatically Generated Cross Bins |
48 |
2 |
46 |
95.83 |
2 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER | STATUS |
[all_values[5]] |
[auto[0]] |
* |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
137 |
1 |
|
|
T58 |
5 |
|
T64 |
4 |
|
T65 |
2 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
74 |
1 |
|
|
T58 |
2 |
|
T64 |
2 |
|
T163 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
119 |
1 |
|
|
T58 |
3 |
|
T64 |
3 |
|
T65 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
77 |
1 |
|
|
T58 |
1 |
|
T64 |
2 |
|
T163 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
151 |
1 |
|
|
T58 |
2 |
|
T64 |
3 |
|
T34 |
1 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
148 |
1 |
|
|
T58 |
4 |
|
T64 |
3 |
|
T34 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
141 |
1 |
|
|
T58 |
2 |
|
T64 |
4 |
|
T65 |
2 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
64 |
1 |
|
|
T34 |
1 |
|
T164 |
2 |
|
T163 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
134 |
1 |
|
|
T58 |
2 |
|
T64 |
1 |
|
T65 |
1 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
76 |
1 |
|
|
T58 |
4 |
|
T64 |
5 |
|
T164 |
1 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
156 |
1 |
|
|
T58 |
5 |
|
T64 |
4 |
|
T65 |
1 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
135 |
1 |
|
|
T58 |
4 |
|
T64 |
3 |
|
T34 |
4 |
all_values[2] |
auto[0] |
auto[0] |
auto[0] |
116 |
1 |
|
|
T58 |
3 |
|
T64 |
1 |
|
T65 |
2 |
all_values[2] |
auto[0] |
auto[0] |
auto[1] |
78 |
1 |
|
|
T58 |
3 |
|
T34 |
3 |
|
T164 |
1 |
all_values[2] |
auto[0] |
auto[1] |
auto[0] |
110 |
1 |
|
|
T58 |
2 |
|
T64 |
6 |
|
T34 |
1 |
all_values[2] |
auto[0] |
auto[1] |
auto[1] |
85 |
1 |
|
|
T58 |
4 |
|
T64 |
1 |
|
T164 |
2 |
all_values[2] |
auto[1] |
auto[0] |
auto[1] |
160 |
1 |
|
|
T58 |
3 |
|
T64 |
2 |
|
T65 |
1 |
all_values[2] |
auto[1] |
auto[1] |
auto[1] |
157 |
1 |
|
|
T58 |
2 |
|
T64 |
7 |
|
T65 |
1 |
all_values[3] |
auto[0] |
auto[0] |
auto[0] |
135 |
1 |
|
|
T58 |
4 |
|
T64 |
3 |
|
T164 |
1 |
all_values[3] |
auto[0] |
auto[0] |
auto[1] |
69 |
1 |
|
|
T58 |
1 |
|
T64 |
2 |
|
T34 |
2 |
all_values[3] |
auto[0] |
auto[1] |
auto[0] |
115 |
1 |
|
|
T58 |
5 |
|
T65 |
1 |
|
T34 |
1 |
all_values[3] |
auto[0] |
auto[1] |
auto[1] |
70 |
1 |
|
|
T58 |
1 |
|
T64 |
2 |
|
T65 |
1 |
all_values[3] |
auto[1] |
auto[0] |
auto[1] |
161 |
1 |
|
|
T58 |
5 |
|
T64 |
7 |
|
T65 |
1 |
all_values[3] |
auto[1] |
auto[1] |
auto[1] |
156 |
1 |
|
|
T58 |
1 |
|
T64 |
3 |
|
T65 |
1 |
all_values[4] |
auto[0] |
auto[0] |
auto[0] |
133 |
1 |
|
|
T58 |
1 |
|
T64 |
3 |
|
T65 |
4 |
all_values[4] |
auto[0] |
auto[0] |
auto[1] |
72 |
1 |
|
|
T64 |
1 |
|
T34 |
1 |
|
T165 |
1 |
all_values[4] |
auto[0] |
auto[1] |
auto[0] |
133 |
1 |
|
|
T58 |
3 |
|
T64 |
2 |
|
T164 |
3 |
all_values[4] |
auto[0] |
auto[1] |
auto[1] |
81 |
1 |
|
|
T58 |
1 |
|
T64 |
3 |
|
T34 |
4 |
all_values[4] |
auto[1] |
auto[0] |
auto[1] |
160 |
1 |
|
|
T58 |
8 |
|
T64 |
6 |
|
T34 |
1 |
all_values[4] |
auto[1] |
auto[1] |
auto[1] |
127 |
1 |
|
|
T58 |
4 |
|
T64 |
2 |
|
T34 |
3 |
all_values[5] |
auto[0] |
auto[0] |
auto[0] |
207 |
1 |
|
|
T58 |
4 |
|
T64 |
6 |
|
T65 |
1 |
all_values[5] |
auto[0] |
auto[1] |
auto[0] |
191 |
1 |
|
|
T58 |
4 |
|
T64 |
4 |
|
T34 |
1 |
all_values[5] |
auto[1] |
auto[0] |
auto[1] |
163 |
1 |
|
|
T58 |
5 |
|
T64 |
4 |
|
T65 |
3 |
all_values[5] |
auto[1] |
auto[1] |
auto[1] |
145 |
1 |
|
|
T58 |
4 |
|
T64 |
3 |
|
T34 |
2 |
all_values[6] |
auto[0] |
auto[0] |
auto[0] |
158 |
1 |
|
|
T58 |
4 |
|
T64 |
3 |
|
T34 |
4 |
all_values[6] |
auto[0] |
auto[0] |
auto[1] |
73 |
1 |
|
|
T58 |
1 |
|
T64 |
3 |
|
T65 |
1 |
all_values[6] |
auto[0] |
auto[1] |
auto[0] |
130 |
1 |
|
|
T58 |
4 |
|
T64 |
1 |
|
T65 |
1 |
all_values[6] |
auto[0] |
auto[1] |
auto[1] |
64 |
1 |
|
|
T58 |
2 |
|
T34 |
1 |
|
T164 |
3 |
all_values[6] |
auto[1] |
auto[0] |
auto[1] |
153 |
1 |
|
|
T58 |
3 |
|
T64 |
3 |
|
T65 |
2 |
all_values[6] |
auto[1] |
auto[1] |
auto[1] |
128 |
1 |
|
|
T58 |
3 |
|
T64 |
7 |
|
T34 |
1 |
all_values[7] |
auto[0] |
auto[0] |
auto[0] |
143 |
1 |
|
|
T58 |
4 |
|
T64 |
6 |
|
T65 |
1 |
all_values[7] |
auto[0] |
auto[0] |
auto[1] |
70 |
1 |
|
|
T58 |
1 |
|
T64 |
1 |
|
T34 |
2 |
all_values[7] |
auto[0] |
auto[1] |
auto[0] |
116 |
1 |
|
|
T58 |
4 |
|
T64 |
4 |
|
T164 |
1 |
all_values[7] |
auto[0] |
auto[1] |
auto[1] |
65 |
1 |
|
|
T58 |
2 |
|
T64 |
2 |
|
T65 |
2 |
all_values[7] |
auto[1] |
auto[0] |
auto[1] |
154 |
1 |
|
|
T58 |
3 |
|
T64 |
2 |
|
T163 |
3 |
all_values[7] |
auto[1] |
auto[1] |
auto[1] |
158 |
1 |
|
|
T58 |
3 |
|
T64 |
2 |
|
T65 |
1 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |