Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2349938	1			T1	75449		T2	1		T3	1
all_values[1]	2349938	1			T1	75449		T2	1		T3	1
all_values[2]	2349938	1			T1	75449		T2	1		T3	1
all_values[3]	2349938	1			T1	75449		T2	1		T3	1
all_values[4]	2349938	1			T1	75449		T2	1		T3	1
all_values[5]	2349938	1			T1	75449		T2	1		T3	1
all_values[6]	2349938	1			T1	75449		T2	1		T3	1
all_values[7]	2349938	1			T1	75449		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18313762

1

T1

603592

T2

8

T3

8

auto[1]

485742

1

T59

62

T56

61

T67

107

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18777881

1

T1

603417

T2

8

T3

8

auto[1]

21623

1

T1

175

T6

2

T14

143

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2289876	1			T1	75314		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11475	1			T1	135		T14	124		T28	18
all_values[0]	auto[1]	auto[0]	48224	1			T59	4		T56	9		T67	11
all_values[0]	auto[1]	auto[1]	363	1			T59	3		T56	3		T67	4
all_values[1]	auto[0]	auto[0]	2280969	1			T1	75409		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5300	1			T1	40		T14	19		T28	18
all_values[1]	auto[1]	auto[0]	63391	1			T59	1		T56	6		T67	4
all_values[1]	auto[1]	auto[1]	278	1			T56	1		T67	12		T68	3
all_values[2]	auto[0]	auto[0]	2259167	1			T1	75449		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2075	1			T59	23		T170	68		T35	26
all_values[2]	auto[1]	auto[0]	88486	1			T59	4		T56	7		T67	4
all_values[2]	auto[1]	auto[1]	210	1			T59	6		T56	5		T67	11
all_values[3]	auto[0]	auto[0]	2247224	1			T1	75449		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	185	1			T59	1		T56	4		T67	12
all_values[3]	auto[1]	auto[0]	102364	1			T59	8		T56	5		T67	5
all_values[3]	auto[1]	auto[1]	165	1			T59	2		T56	2		T67	7
all_values[4]	auto[0]	auto[0]	2296849	1			T1	75449		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	178	1			T59	4		T67	6		T68	1
all_values[4]	auto[1]	auto[0]	52700	1			T59	5		T56	4		T67	6
all_values[4]	auto[1]	auto[1]	211	1			T59	3		T67	8		T68	2
all_values[5]	auto[0]	auto[0]	2309069	1			T1	75449		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	287	1			T6	2		T16	3		T59	1
all_values[5]	auto[1]	auto[0]	40435	1			T59	6		T56	4		T67	3
all_values[5]	auto[1]	auto[1]	147	1			T59	1		T56	4		T67	4
all_values[6]	auto[0]	auto[0]	2274353	1			T1	75449		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	207	1			T59	1		T67	7		T68	2
all_values[6]	auto[1]	auto[0]	75217	1			T59	7		T56	1		T67	10
all_values[6]	auto[1]	auto[1]	161	1			T59	3		T56	4		T67	5
all_values[7]	auto[0]	auto[0]	2336339	1			T1	75449		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	209	1			T59	2		T56	3		T67	10
all_values[7]	auto[1]	auto[0]	13218	1			T59	8		T56	5		T67	5
all_values[7]	auto[1]	auto[1]	172	1			T59	1		T56	1		T67	8