Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32987	1			T1	107		T2	6		T3	6
auto[SpiFlashAddrCfg]	6823	1			T1	63		T3	8		T7	16
auto[SpiFlashAddr3b]	8260	1			T1	60		T3	8		T7	19
auto[SpiFlashAddr4b]	6727	1			T1	61		T7	11		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31401

1

T1

170

T2

6

T3

22

auto[1]

23396

1

T1

121

T7

44

T11

12

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28803

1

T1

164

T2

6

T3

12

auto[1]

25994

1

T1

127

T3

10

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37147	1			T1	146		T2	6		T3	12
values[1]	874	1			T1	4		T7	1		T43	2
values[2]	1343	1			T1	6		T7	3		T10	6
values[3]	1444	1			T1	14		T7	3		T11	2
values[4]	1317	1			T1	12		T7	5		T11	2
values[5]	1306	1			T1	12		T7	5		T10	2
values[6]	1288	1			T1	5		T7	3		T20	8
values[7]	1328	1			T1	8		T7	5		T11	4
values[8]	8750	1			T1	84		T3	10		T7	16

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26135

1

T1

291

T2

6

T3

22

auto[1]

28662

1

T7

194

T20

261

T38

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52935

1

T1

284

T2

6

T3

22

write

1862

1

T1

7

T7

2

T20

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17947

1

T1

163

T2

6

T3

14

valids[0x1]

36850

1

T1

128

T3

8

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1468	1			T1	9		T4	2		T7	2
internal_process_ops[0x5a]	1478	1			T1	9		T7	2		T9	2
internal_process_ops[0x05]	20266	1			T1	16		T7	117		T10	4
internal_process_ops[0x35]	1390	1			T1	12		T3	2		T4	4
internal_process_ops[0x15]	1467	1			T1	9		T4	2		T7	4
internal_process_ops[0x03]	917	1			T1	7		T7	3		T9	2
internal_process_ops[0x0b]	895	1			T1	10		T9	2		T20	1
internal_process_ops[0x3b]	948	1			T1	15		T19	2		T43	2
internal_process_ops[0x6b]	909	1			T1	14		T10	2		T11	2
internal_process_ops[0xbb]	982	1			T1	6		T7	2		T10	6
internal_process_ops[0xeb]	979	1			T1	6		T7	2		T20	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53920

1

T1

288

T2

6

T3

22

auto[1]

877

1

T1

3

T20

5

T27

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52968

1

T1

282

T2

6

T3

22

auto[1]

1829

1

T1

9

T7

8

T20

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8572

1

T1

63

T2

6

T3

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5507

1

T1

42

T11

2

T27

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1888

1

T1

26

T3

8

T9

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1603

1

T1

35

T14

14

T28

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2266

1

T1

36

T3

8

T9

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2060

1

T1

24

T11

2

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1888

1

T1

38

T9

2

T14

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1539

1

T1

20

T11

8

T27

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T1

2

T33

2

T47

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T30

1

T33

2

T166

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

39

1

T14

1

T35

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

53

1

T34

4

T36

4

T166

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

67

1

T1

1

T30

1

T167

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

41

1

T1

1

T31

1

T32

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

46

1

T33

2

T35

2

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

61

1

T33

1

T35

4

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

48

1

T35

3

T36

1

T84

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T28

2

T36

1

T84

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

42

1

T14

3

T30

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T32

1

T35

1

T168

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

66

1

T1

1

T28

1

T30

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

40

1

T1

2

T27

1

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

40

1

T84

4

T152

1

T164

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

47

1

T28

1

T35

1

T36

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11105

1

T7

127

T20

106

T21

12

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7335

1

T7

19

T20

77

T21

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1511

1

T7

8

T20

14

T38

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1388

1

T7

8

T20

6

T21

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1786

1

T7

12

T20

18

T21

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1703

1

T7

7

T20

14

T21

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1401

1

T7

3

T20

11

T38

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1383

1

T7

8

T20

5

T21

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

79

1

T59

2

T137

1

T169

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

55

1

T59

2

T137

1

T58

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

69

1

T7

2

T21

1

T59

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

60

1

T20

1

T59

1

T137

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T20

3

T59

3

T58

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

43

1

T59

3

T169

1

T67

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

62

1

T83

1

T170

2

T169

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

47

1

T21

1

T67

1

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T21

1

T56

1

T58

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

59

1

T59

5

T137

2

T164

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T20

2

T83

4

T171

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

44

1

T59

1

T170

1

T56

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

86

1

T21

1

T169

4

T56

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T20

2

T59

1

T137

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

66

1

T59

1

T83

2

T170

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

70

1

T20

2

T59

1

T170

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3670	1			T1	59		T2	6		T3	4
auto[0]	values[0]	valids[0x1]	12777	1			T1	87		T3	8		T4	8
auto[0]	values[1]	valids[0x1]	400	1			T1	4		T43	2		T27	1
auto[0]	values[2]	valids[0x0]	475	1			T1	5		T10	6		T27	2
auto[0]	values[2]	valids[0x1]	287	1			T1	1		T14	4		T15	1
auto[0]	values[3]	valids[0x0]	516	1			T1	10		T11	2		T14	6
auto[0]	values[3]	valids[0x1]	296	1			T1	4		T14	7		T30	9
auto[0]	values[4]	valids[0x0]	470	1			T1	10		T14	7		T30	3
auto[0]	values[4]	valids[0x1]	223	1			T1	2		T11	2		T27	1
auto[0]	values[5]	valids[0x0]	463	1			T1	11		T10	2		T14	9
auto[0]	values[5]	valids[0x1]	262	1			T1	1		T30	6		T31	3
auto[0]	values[6]	valids[0x0]	473	1			T1	5		T27	1		T14	8
auto[0]	values[6]	valids[0x1]	269	1			T14	3		T15	2		T28	1
auto[0]	values[7]	valids[0x0]	471	1			T1	4		T11	4		T14	10
auto[0]	values[7]	valids[0x1]	260	1			T1	4		T27	1		T14	4
auto[0]	values[8]	valids[0x0]	3033	1			T1	59		T3	10		T11	2
auto[0]	values[8]	valids[0x1]	1790	1			T1	25		T9	4		T12	2
auto[1]	values[0]	valids[0x0]	3933	1			T7	19		T20	35		T21	14
auto[1]	values[0]	valids[0x1]	16767	1			T7	134		T20	167		T38	2
auto[1]	values[1]	valids[0x1]	474	1			T7	1		T20	2		T38	2
auto[1]	values[2]	valids[0x0]	363	1			T7	2		T20	3		T21	1
auto[1]	values[2]	valids[0x1]	218	1			T7	1		T20	2		T21	2
auto[1]	values[3]	valids[0x0]	346	1			T20	5		T21	3		T59	5
auto[1]	values[3]	valids[0x1]	286	1			T7	3		T21	2		T59	5
auto[1]	values[4]	valids[0x0]	381	1			T7	5		T20	4		T38	1
auto[1]	values[4]	valids[0x1]	243	1			T21	4		T59	4		T83	4
auto[1]	values[5]	valids[0x0]	351	1			T7	3		T20	2		T38	1
auto[1]	values[5]	valids[0x1]	230	1			T7	2		T20	2		T59	3
auto[1]	values[6]	valids[0x0]	326	1			T20	2		T172	1		T21	2
auto[1]	values[6]	valids[0x1]	220	1			T7	3		T20	6		T59	3
auto[1]	values[7]	valids[0x0]	348	1			T7	3		T20	3		T38	3
auto[1]	values[7]	valids[0x1]	249	1			T7	2		T20	5		T59	2
auto[1]	values[8]	valids[0x0]	2328	1			T7	11		T20	14		T39	2
auto[1]	values[8]	valids[0x1]	1599	1			T7	5		T20	9		T21	5