Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3230827

1

T1

14882

T2

713

T3

1

auto[1]

18840

1

T1

11

T7

114

T20

121

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075794

1

T1

74

T2

713

T3

1

auto[1]

2173873

1

T1

14819

T4

4246

T7

3890

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	724192	1			T1	1756		T2	118		T3	1
auto[524288:1048575]	394497	1			T1	4025		T4	5265		T7	1460
auto[1048576:1572863]	373492	1			T1	1669		T2	240		T4	911
auto[1572864:2097151]	329748	1			T1	270		T4	1616		T7	386
auto[2097152:2621439]	355458	1			T1	19		T7	287		T43	5408
auto[2621440:3145727]	326472	1			T1	21		T4	871		T7	512
auto[3145728:3670015]	400537	1			T1	3648		T2	2		T4	400
auto[3670016:4194303]	345271	1			T1	3485		T2	353		T4	1096

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2193358

1

T1

14893

T2

128

T3

1

auto[1]

1056309

1

T2

585

T4

8378

T7

8

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2874500

1

T1

12623

T2

713

T3

1

auto[1]

375167

1

T1

2270

T7

2669

T20

1209

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	236243	1			T1	2		T2	118		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	417016	1			T1	5		T4	2085		T7	513
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	128336	1			T1	7		T4	3525		T7	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	229117	1			T1	3758		T4	1740		T7	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	116650	1			T1	5		T2	240		T4	891
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	218321	1			T1	1664		T4	20		T14	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	115556	1			T1	4		T4	1358		T7	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	165655	1			T1	265		T4	258		T7	384
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116501	1			T1	10		T7	1		T43	5408
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	187529	1			T1	5		T7	257		T20	662
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	87795	1			T1	16		T4	728		T9	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	192746	1			T1	4		T4	143		T20	1283
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	156574	1			T1	8		T2	2		T4	400
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	186613	1			T1	3638		T7	2		T20	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	106463	1			T1	8		T2	353		T4	1096
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	198583	1			T1	3214		T7	1		T20	384
auto[0]	auto[1]	auto[0:524287]	auto[0]	1591	1			T1	1		T28	2		T30	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	66547	1			T1	1748		T30	2760		T59	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1013	1			T7	3		T14	1		T30	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	33862	1			T1	259		T7	1446		T28	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	483	1			T28	1		T33	2		T35	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	36048	1			T14	256		T31	3		T59	1646
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1371	1			T20	2		T28	1		T59	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	44835	1			T20	512		T59	252		T83	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1155	1			T7	3		T20	1		T30	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48335	1			T7	1		T20	664		T30	1007
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	702	1			T14	1		T30	2		T31	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	42813	1			T7	512		T30	1		T31	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2861	1			T7	7		T30	1		T31	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	51641	1			T7	641		T31	2228		T59	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	664	1			T1	4		T7	1		T14	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	37208	1			T1	257		T7	26		T14	6
auto[1]	auto[0]	auto[0:524287]	auto[0]	224	1			T7	1		T28	1		T31	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	1992	1			T7	7		T28	4		T31	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	169	1			T1	1		T7	1		T20	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1644	1			T7	8		T20	40		T30	53
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	159	1			T14	4		T31	1		T33	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1443	1			T33	4		T83	5		T35	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	163	1			T1	1		T31	1		T32	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1489	1			T32	3		T137	1		T36	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	168	1			T1	2		T20	1		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1258	1			T1	2		T20	19		T27	14
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	213	1			T1	1		T20	3		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1785	1			T20	26		T14	2		T30	24
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	181	1			T1	2		T7	2		T30	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1981	1			T7	60		T30	54		T59	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	180	1			T1	1		T7	1		T14	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1753	1			T7	5		T14	9		T28	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	61	1			T30	1		T33	1		T83	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	518	1			T30	34		T33	1		T83	13
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	40	1			T30	1		T169	1		T211	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	316	1			T30	20		T244	9		T245	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	31	1			T35	3		T84	1		T152	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	357	1			T35	1		T152	6		T246	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	54	1			T59	3		T83	1		T137	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	625	1			T59	9		T83	3		T137	65
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	60	1			T7	1		T20	1		T30	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	452	1			T7	24		T20	29		T30	63
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	38	1			T30	1		T31	1		T35	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	380	1			T30	6		T31	18		T36	22
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	49	1			T7	1		T59	1		T83	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	637	1			T7	2		T59	5		T83	31
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	46	1			T1	1		T7	1		T14	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	374	1			T14	1		T83	10		T137	50

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1811210	1			T1	12613		T2	128		T3	1
auto[0]	auto[0]	auto[1]	1048488	1			T2	585		T4	8378		T7	5
auto[0]	auto[1]	auto[0]	363660	1			T1	2269		T7	2638		T20	1179
auto[0]	auto[1]	auto[1]	7469	1			T7	2		T30	3		T31	1
auto[1]	auto[0]	auto[0]	14512	1			T1	10		T7	84		T20	86
auto[1]	auto[0]	auto[1]	290	1			T7	1		T20	5		T27	1
auto[1]	auto[1]	auto[0]	3976	1			T1	1		T7	29		T20	30
auto[1]	auto[1]	auto[1]	62	1			T30	1		T31	1		T83	4