Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15044

1

T1

170

T2

6

T3

22

auto[1]

11091

1

T1

121

T11

12

T12

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3754	1			T1	42		T2	6		T43	4
values[1]	2601	1			T1	62		T9	6		T11	12
values[2]	3213	1			T1	62		T4	8		T10	14
values[3]	3262	1			T1	21		T44	6		T30	139
values[4]	3141	1			T1	40		T19	6		T14	22
values[5]	2979	1			T1	24		T3	22		T27	35
values[6]	3713	1			T1	20		T14	47		T30	67
values[7]	3472	1			T1	20		T12	2		T15	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3017	1			T1	20		T11	12		T14	20
values[1]	3247	1			T3	22		T4	8		T14	42
values[2]	3367	1			T1	62		T43	4		T14	41
values[3]	2977	1			T1	42		T10	14		T19	6
values[4]	3206	1			T1	61		T14	28		T28	23
values[5]	3671	1			T1	24		T2	6		T12	2
values[6]	3768	1			T1	62		T9	6		T14	20
values[7]	2882	1			T1	20		T14	26		T30	83

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	206	1			T14	13		T28	17		T160	13
auto[0]	values[0]	values[1]	339	1			T30	16		T36	56		T247	16
auto[0]	values[0]	values[2]	240	1			T43	4		T14	11		T248	21
auto[0]	values[0]	values[3]	224	1			T1	12		T30	13		T31	7
auto[0]	values[0]	values[4]	286	1			T1	13		T30	14		T95	26
auto[0]	values[0]	values[5]	269	1			T2	6		T33	13		T84	13
auto[0]	values[0]	values[6]	300	1			T30	11		T36	10		T52	8
auto[0]	values[0]	values[7]	197	1			T35	14		T164	7		T249	18
auto[0]	values[1]	values[0]	305	1			T250	12		T35	16		T166	81
auto[0]	values[1]	values[1]	186	1			T226	18		T251	2		T152	31
auto[0]	values[1]	values[2]	248	1			T1	40		T31	17		T238	4
auto[0]	values[1]	values[3]	98	1			T31	12		T35	10		T84	15
auto[0]	values[1]	values[4]	146	1			T14	16		T30	8		T220	20
auto[0]	values[1]	values[5]	134	1			T14	33		T252	10		T197	12
auto[0]	values[1]	values[6]	198	1			T9	6		T14	14		T160	15
auto[0]	values[1]	values[7]	155	1			T159	20		T253	12		T254	10
auto[0]	values[2]	values[0]	308	1			T186	10		T255	10		T191	16
auto[0]	values[2]	values[1]	200	1			T4	8		T256	4		T186	14
auto[0]	values[2]	values[2]	141	1			T84	15		T257	2		T221	30
auto[0]	values[2]	values[3]	303	1			T10	14		T31	9		T32	22
auto[0]	values[2]	values[4]	199	1			T76	20		T68	18		T197	9
auto[0]	values[2]	values[5]	246	1			T167	18		T136	12		T209	31
auto[0]	values[2]	values[6]	437	1			T1	37		T84	14		T164	20
auto[0]	values[2]	values[7]	204	1			T30	12		T205	8		T258	10
auto[0]	values[3]	values[0]	84	1			T259	4		T152	12		T49	13
auto[0]	values[3]	values[1]	315	1			T30	13		T166	10		T260	18
auto[0]	values[3]	values[2]	173	1			T30	6		T35	13		T166	26
auto[0]	values[3]	values[3]	234	1			T1	10		T44	6		T33	10
auto[0]	values[3]	values[4]	219	1			T119	16		T31	11		T33	12
auto[0]	values[3]	values[5]	308	1			T30	30		T84	21		T210	4
auto[0]	values[3]	values[6]	150	1			T166	11		T198	26		T139	15
auto[0]	values[3]	values[7]	197	1			T31	15		T36	12		T211	13
auto[0]	values[4]	values[0]	231	1			T1	13		T30	17		T80	6
auto[0]	values[4]	values[1]	127	1			T14	12		T32	7		T33	10
auto[0]	values[4]	values[2]	265	1			T233	24		T261	4		T232	16
auto[0]	values[4]	values[3]	97	1			T19	6		T262	2		T194	28
auto[0]	values[4]	values[4]	229	1			T1	8		T166	29		T47	6
auto[0]	values[4]	values[5]	258	1			T31	12		T33	13		T36	14
auto[0]	values[4]	values[6]	434	1			T47	13		T199	24		T211	22
auto[0]	values[4]	values[7]	267	1			T75	6		T166	6		T84	14
auto[0]	values[5]	values[0]	144	1			T35	11		T224	12		T263	4
auto[0]	values[5]	values[1]	342	1			T3	22		T14	14		T36	14
auto[0]	values[5]	values[2]	293	1			T194	14		T264	4		T49	16
auto[0]	values[5]	values[3]	160	1			T152	33		T211	13		T140	12
auto[0]	values[5]	values[4]	276	1			T28	17		T91	6		T35	9
auto[0]	values[5]	values[5]	220	1			T1	10		T27	10		T265	6
auto[0]	values[5]	values[6]	126	1			T241	2		T152	8		T213	20
auto[0]	values[5]	values[7]	198	1			T31	11		T185	22		T35	13
auto[0]	values[6]	values[0]	330	1			T81	16		T84	34		T209	14
auto[0]	values[6]	values[1]	291	1			T35	9		T54	18		T266	18
auto[0]	values[6]	values[2]	275	1			T14	14		T30	7		T166	9
auto[0]	values[6]	values[3]	167	1			T35	9		T218	12		T152	26
auto[0]	values[6]	values[4]	161	1			T37	12		T181	20		T152	10
auto[0]	values[6]	values[5]	243	1			T267	4		T184	10		T49	9
auto[0]	values[6]	values[6]	241	1			T30	12		T31	2		T186	9
auto[0]	values[6]	values[7]	333	1			T1	13		T14	13		T32	31
auto[0]	values[7]	values[0]	246	1			T84	13		T47	11		T186	11
auto[0]	values[7]	values[1]	177	1			T33	14		T201	4		T197	7
auto[0]	values[7]	values[2]	274	1			T47	14		T58	10		T164	9
auto[0]	values[7]	values[3]	419	1			T15	9		T187	14		T186	8
auto[0]	values[7]	values[4]	447	1			T1	14		T35	14		T84	29
auto[0]	values[7]	values[5]	176	1			T32	10		T35	13		T166	12
auto[0]	values[7]	values[6]	250	1			T36	81		T152	7		T194	21
auto[0]	values[7]	values[7]	98	1			T268	2		T197	9		T269	23
auto[1]	values[0]	values[0]	110	1			T14	7		T28	8		T160	7
auto[1]	values[0]	values[1]	208	1			T30	4		T36	10		T211	12
auto[1]	values[0]	values[2]	111	1			T14	9		T248	1		T140	13
auto[1]	values[0]	values[3]	306	1			T1	9		T30	42		T31	16
auto[1]	values[0]	values[4]	203	1			T1	8		T30	25		T198	5
auto[1]	values[0]	values[5]	194	1			T33	7		T84	8		T164	14
auto[1]	values[0]	values[6]	329	1			T30	75		T36	12		T186	16
auto[1]	values[0]	values[7]	232	1			T35	8		T164	13		T270	22
auto[1]	values[1]	values[0]	169	1			T11	12		T35	6		T166	10
auto[1]	values[1]	values[1]	135	1			T152	6		T139	37		T140	16
auto[1]	values[1]	values[2]	172	1			T1	22		T31	3		T197	8
auto[1]	values[1]	values[3]	127	1			T31	12		T35	21		T84	5
auto[1]	values[1]	values[4]	184	1			T14	12		T30	77		T35	13
auto[1]	values[1]	values[5]	165	1			T14	10		T197	8		T271	9
auto[1]	values[1]	values[6]	95	1			T14	6		T160	13		T162	10
auto[1]	values[1]	values[7]	84	1			T34	16		T254	11		T194	7
auto[1]	values[2]	values[0]	203	1			T186	10		T139	6		T140	15
auto[1]	values[2]	values[1]	115	1			T186	7		T208	7		T182	17
auto[1]	values[2]	values[2]	62	1			T84	6		T221	20		T272	8
auto[1]	values[2]	values[3]	134	1			T31	11		T32	2		T84	13
auto[1]	values[2]	values[4]	76	1			T68	7		T197	11		T182	6
auto[1]	values[2]	values[5]	157	1			T209	15		T140	7		T182	10
auto[1]	values[2]	values[6]	281	1			T1	25		T84	6		T164	10
auto[1]	values[2]	values[7]	147	1			T30	71		T139	20		T273	7
auto[1]	values[3]	values[0]	58	1			T152	8		T274	14		T49	7
auto[1]	values[3]	values[1]	292	1			T30	57		T166	35		T47	6
auto[1]	values[3]	values[2]	297	1			T30	22		T35	11		T166	21
auto[1]	values[3]	values[3]	238	1			T1	11		T33	29		T211	7
auto[1]	values[3]	values[4]	90	1			T31	9		T33	8		T152	12
auto[1]	values[3]	values[5]	155	1			T30	11		T84	4		T194	11
auto[1]	values[3]	values[6]	235	1			T166	9		T198	110		T139	5
auto[1]	values[3]	values[7]	217	1			T31	5		T132	22		T36	8
auto[1]	values[4]	values[0]	146	1			T1	7		T30	10		T47	8
auto[1]	values[4]	values[1]	121	1			T14	10		T32	13		T33	10
auto[1]	values[4]	values[2]	195	1			T275	6		T198	14		T139	55
auto[1]	values[4]	values[3]	41	1			T194	18		T140	14		T276	5
auto[1]	values[4]	values[4]	235	1			T1	12		T166	9		T47	27
auto[1]	values[4]	values[5]	201	1			T31	27		T33	7		T36	7
auto[1]	values[4]	values[6]	155	1			T47	10		T211	4		T154	13
auto[1]	values[4]	values[7]	139	1			T166	14		T84	6		T209	11
auto[1]	values[5]	values[0]	174	1			T277	4		T35	10		T211	2
auto[1]	values[5]	values[1]	116	1			T14	6		T36	6		T166	8
auto[1]	values[5]	values[2]	146	1			T194	9		T49	5		T208	10
auto[1]	values[5]	values[3]	95	1			T152	7		T211	7		T140	9
auto[1]	values[5]	values[4]	142	1			T28	6		T35	13		T49	8
auto[1]	values[5]	values[5]	301	1			T1	14		T27	25		T47	18
auto[1]	values[5]	values[6]	127	1			T152	61		T213	5		T271	15
auto[1]	values[5]	values[7]	119	1			T31	10		T35	7		T36	47
auto[1]	values[6]	values[0]	154	1			T81	4		T84	17		T209	6
auto[1]	values[6]	values[1]	159	1			T35	11		T194	8		T278	8
auto[1]	values[6]	values[2]	286	1			T14	7		T30	40		T166	76
auto[1]	values[6]	values[3]	135	1			T35	13		T152	4		T140	14
auto[1]	values[6]	values[4]	108	1			T152	10		T221	7		T279	21
auto[1]	values[6]	values[5]	367	1			T280	12		T168	22		T237	6
auto[1]	values[6]	values[6]	210	1			T30	8		T31	18		T186	11
auto[1]	values[6]	values[7]	253	1			T1	7		T14	13		T32	13
auto[1]	values[7]	values[0]	149	1			T84	8		T47	9		T186	9
auto[1]	values[7]	values[1]	124	1			T33	8		T197	14		T208	11
auto[1]	values[7]	values[2]	189	1			T47	9		T58	14		T164	11
auto[1]	values[7]	values[3]	199	1			T15	11		T186	12		T212	7
auto[1]	values[7]	values[4]	205	1			T1	6		T35	6		T84	4
auto[1]	values[7]	values[5]	277	1			T12	2		T32	14		T35	8
auto[1]	values[7]	values[6]	200	1			T36	8		T152	14		T194	19
auto[1]	values[7]	values[7]	42	1			T197	11		T269	11		T88	5