Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	357	1			T1	5		T9	2		T14	2
auto[ReadAddrCrossIntoMailbox]	261	1			T1	2		T14	3		T30	4
auto[ReadAddrCrossOutOfMailbox]	286	1			T1	7		T43	2		T14	4
auto[ReadAddrCrossAllMailbox]	175	1			T1	4		T14	5		T30	2
auto[ReadAddrOutsideMailbox]	3063	1			T1	40		T9	2		T10	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2053

1

T1

25

T9

2

T10

4

auto[1]

2089

1

T1

33

T9

2

T10

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	674	1			T1	7		T9	2		T27	1
read_ops[0x0b]	647	1			T1	10		T9	2		T27	1
read_ops[0x3b]	705	1			T1	15		T19	2		T43	2
read_ops[0x6b]	660	1			T1	14		T10	2		T11	2
read_ops[0xbb]	723	1			T1	6		T10	6		T44	4
read_ops[0xeb]	733	1			T1	6		T14	12		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T220	1		T91	3		T76	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T220	1		T33	1		T91	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T218	1		T152	1		T282	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T1	1		T14	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T14	1		T30	1		T220	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T220	1		T33	1		T75	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T1	1		T166	1		T282	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T282	1		T140	1		T271	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T1	2		T9	1		T27	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T1	3		T9	1		T14	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T1	1		T9	1		T30	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T9	1		T28	1		T36	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T1	1		T33	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T32	1		T166	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T1	1		T33	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T36	1		T84	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T1	1		T271	1		T276	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T166	2		T84	1		T211	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	222	1			T1	3		T14	3		T30	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T1	3		T27	1		T14	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T152	1		T196	1		T164	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T14	1		T28	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T31	1		T232	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T14	1		T31	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T1	1		T43	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T1	3		T43	1		T30	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T31	1		T166	1		T58	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T14	1		T166	1		T160	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T1	3		T19	1		T14	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T1	8		T19	1		T14	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T1	1		T32	1		T166	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T1	3		T36	1		T186	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T166	1		T84	1		T232	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T30	3		T35	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T14	2		T81	1		T68	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T1	1		T31	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T232	1		T194	2		T283	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T232	1		T254	1		T49	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T1	2		T10	1		T11	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T1	7		T10	1		T11	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T166	2		T200	1		T139	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T35	1		T84	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T232	1		T186	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T31	1		T232	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T31	1		T32	1		T84	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T166	2		T160	1		T232	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T1	1		T14	2		T166	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T1	1		T14	1		T30	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T1	2		T10	3		T44	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T1	2		T10	3		T44	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T14	1		T31	1		T220	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T31	1		T220	1		T76	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T218	1		T186	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T14	1		T166	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T14	1		T31	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T1	1		T218	1		T152	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T14	1		T36	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T32	1		T166	1		T47	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T1	5		T14	2		T119	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	257	1			T14	6		T15	2		T28	1