Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2349938	1			T1	75449		T2	1		T3	1
all_pins[1]	2349938	1			T1	75449		T2	1		T3	1
all_pins[2]	2349938	1			T1	75449		T2	1		T3	1
all_pins[3]	2349938	1			T1	75449		T2	1		T3	1
all_pins[4]	2349938	1			T1	75449		T2	1		T3	1
all_pins[5]	2349938	1			T1	75449		T2	1		T3	1
all_pins[6]	2349938	1			T1	75449		T2	1		T3	1
all_pins[7]	2349938	1			T1	75449		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18723195	1			T1	603592		T2	8		T3	8
values[0x1]	76309	1			T59	19		T56	20		T67	59
transitions[0x0=>0x1]	75438	1			T59	18		T56	17		T67	40
transitions[0x1=>0x0]	75448	1			T59	18		T56	17		T67	40

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2349539	1			T1	75449		T2	1		T3	1
all_pins[0]	values[0x1]	399	1			T59	3		T56	3		T67	4
all_pins[0]	transitions[0x0=>0x1]	314	1			T59	3		T56	3		T68	1
all_pins[0]	transitions[0x1=>0x0]	220	1			T56	1		T67	8		T68	3
all_pins[1]	values[0x0]	2349633	1			T1	75449		T2	1		T3	1
all_pins[1]	values[0x1]	305	1			T56	1		T67	12		T68	3
all_pins[1]	transitions[0x0=>0x1]	220	1			T56	1		T67	6		T68	1
all_pins[1]	transitions[0x1=>0x0]	129	1			T59	6		T56	5		T67	5
all_pins[2]	values[0x0]	2349724	1			T1	75449		T2	1		T3	1
all_pins[2]	values[0x1]	214	1			T59	6		T56	5		T67	11
all_pins[2]	transitions[0x0=>0x1]	165	1			T59	6		T56	4		T67	9
all_pins[2]	transitions[0x1=>0x0]	116	1			T59	2		T56	1		T67	5
all_pins[3]	values[0x0]	2349773	1			T1	75449		T2	1		T3	1
all_pins[3]	values[0x1]	165	1			T59	2		T56	2		T67	7
all_pins[3]	transitions[0x0=>0x1]	117	1			T59	2		T56	2		T67	6
all_pins[3]	transitions[0x1=>0x0]	163	1			T59	3		T67	7		T68	1
all_pins[4]	values[0x0]	2349727	1			T1	75449		T2	1		T3	1
all_pins[4]	values[0x1]	211	1			T59	3		T67	8		T68	2
all_pins[4]	transitions[0x0=>0x1]	171	1			T59	3		T67	6		T68	2
all_pins[4]	transitions[0x1=>0x0]	562	1			T59	1		T56	4		T67	2
all_pins[5]	values[0x0]	2349336	1			T1	75449		T2	1		T3	1
all_pins[5]	values[0x1]	602	1			T59	1		T56	4		T67	4
all_pins[5]	transitions[0x0=>0x1]	118	1			T56	3		T67	3		T68	1
all_pins[5]	transitions[0x1=>0x0]	73757	1			T59	2		T56	3		T67	4
all_pins[6]	values[0x0]	2275697	1			T1	75449		T2	1		T3	1
all_pins[6]	values[0x1]	74241	1			T59	3		T56	4		T67	5
all_pins[6]	transitions[0x0=>0x1]	74205	1			T59	3		T56	3		T67	4
all_pins[6]	transitions[0x1=>0x0]	136	1			T59	1		T67	7		T68	2
all_pins[7]	values[0x0]	2349766	1			T1	75449		T2	1		T3	1
all_pins[7]	values[0x1]	172	1			T59	1		T56	1		T67	8
all_pins[7]	transitions[0x0=>0x1]	128	1			T59	1		T56	1		T67	6
all_pins[7]	transitions[0x1=>0x0]	365	1			T59	3		T56	3		T67	2