Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2953	1			T1	64		T11	12		T28	25
values[1]	3224	1			T1	20		T14	47		T28	23
values[2]	2951	1			T1	20		T2	6		T14	22
values[3]	3377	1			T1	42		T19	6		T27	35
values[4]	3389	1			T1	63		T4	8		T10	14
values[5]	3454	1			T1	21		T12	2		T14	43
values[6]	3317	1			T1	41		T3	22		T43	4
values[7]	3470	1			T1	20		T9	6		T44	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3330	1			T11	12		T14	42		T30	47
values[1]	3299	1			T43	4		T14	20		T30	129
values[2]	2988	1			T1	22		T14	20		T28	25
values[3]	3657	1			T1	41		T9	6		T44	6
values[4]	2965	1			T1	20		T2	6		T3	22
values[5]	3204	1			T1	81		T4	8		T10	14
values[6]	3518	1			T1	42		T14	23		T28	23
values[7]	3174	1			T1	85		T12	2		T19	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25737

1

T1

288

T2

6

T3

22

auto[1]

398

1

T1

3

T27

1

T14

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	443	1			T11	12		T187	14		T35	21
auto[0]	values[0]	values[1]	297	1			T30	20		T31	20		T247	16
auto[0]	values[0]	values[2]	302	1			T28	25		T210	4		T252	10
auto[0]	values[0]	values[3]	397	1			T33	20		T166	20		T254	20
auto[0]	values[0]	values[4]	398	1			T261	4		T201	4		T284	2
auto[0]	values[0]	values[5]	349	1			T1	19		T36	80		T166	27
auto[0]	values[0]	values[6]	415	1			T91	6		T251	2		T194	20
auto[0]	values[0]	values[7]	311	1			T1	44		T254	21		T197	41
auto[0]	values[1]	values[0]	354	1			T167	18		T47	33		T58	23
auto[0]	values[1]	values[1]	421	1			T84	21		T197	25		T285	12
auto[0]	values[1]	values[2]	352	1			T84	24		T139	20		T273	68
auto[0]	values[1]	values[3]	260	1			T1	20		T84	20		T186	20
auto[0]	values[1]	values[4]	303	1			T277	4		T164	20		T255	10
auto[0]	values[1]	values[5]	432	1			T31	20		T37	12		T35	22
auto[0]	values[1]	values[6]	556	1			T28	20		T30	28		T171	27
auto[0]	values[1]	values[7]	479	1			T14	47		T32	21		T84	20
auto[0]	values[2]	values[0]	559	1			T14	22		T33	21		T35	21
auto[0]	values[2]	values[1]	292	1			T84	20		T211	46		T229	10
auto[0]	values[2]	values[2]	402	1			T220	20		T185	22		T162	10
auto[0]	values[2]	values[3]	452	1			T30	85		T119	16		T152	20
auto[0]	values[2]	values[4]	343	1			T1	20		T2	6		T36	22
auto[0]	values[2]	values[5]	270	1			T36	86		T47	18		T237	4
auto[0]	values[2]	values[6]	429	1			T30	85		T265	6		T218	12
auto[0]	values[2]	values[7]	171	1			T35	21		T200	8		T275	6
auto[0]	values[3]	values[0]	461	1			T32	20		T186	21		T198	51
auto[0]	values[3]	values[1]	426	1			T30	70		T32	23		T33	20
auto[0]	values[3]	values[2]	411	1			T47	89		T152	38		T139	82
auto[0]	values[3]	values[3]	726	1			T14	26		T159	20		T194	19
auto[0]	values[3]	values[4]	309	1			T27	34		T160	20		T232	16
auto[0]	values[3]	values[5]	191	1			T1	20		T280	12		T196	8
auto[0]	values[3]	values[6]	414	1			T1	22		T32	23		T36	19
auto[0]	values[3]	values[7]	387	1			T19	6		T55	12		T139	59
auto[0]	values[4]	values[0]	246	1			T30	27		T260	18		T164	30
auto[0]	values[4]	values[1]	209	1			T84	25		T286	4		T139	20
auto[0]	values[4]	values[2]	312	1			T1	21		T209	20		T139	33
auto[0]	values[4]	values[3]	437	1			T34	12		T76	20		T166	85
auto[0]	values[4]	values[4]	510	1			T287	2		T164	20		T139	20
auto[0]	values[4]	values[5]	680	1			T4	8		T10	14		T14	20
auto[0]	values[4]	values[6]	441	1			T1	20		T84	20		T288	12
auto[0]	values[4]	values[7]	490	1			T1	20		T32	22		T33	20
auto[0]	values[5]	values[0]	363	1			T241	2		T84	33		T160	28
auto[0]	values[5]	values[1]	533	1			T30	38		T31	39		T152	20
auto[0]	values[5]	values[2]	459	1			T14	20		T166	38		T289	4
auto[0]	values[5]	values[3]	353	1			T1	21		T31	20		T224	12
auto[0]	values[5]	values[4]	303	1			T31	44		T198	20		T290	2
auto[0]	values[5]	values[5]	541	1			T30	83		T31	23		T80	6
auto[0]	values[5]	values[6]	259	1			T14	23		T58	21		T205	8
auto[0]	values[5]	values[7]	598	1			T12	2		T36	19		T211	22
auto[0]	values[6]	values[0]	366	1			T30	20		T249	18		T291	6
auto[0]	values[6]	values[1]	477	1			T43	4		T35	29		T152	20
auto[0]	values[6]	values[2]	333	1			T35	20		T166	20		T58	27
auto[0]	values[6]	values[3]	600	1			T30	41		T233	24		T35	20
auto[0]	values[6]	values[4]	413	1			T3	22		T15	20		T259	4
auto[0]	values[6]	values[5]	393	1			T1	41		T168	18		T266	18
auto[0]	values[6]	values[6]	408	1			T36	19		T47	22		T152	19
auto[0]	values[6]	values[7]	277	1			T14	20		T292	2		T293	2
auto[0]	values[7]	values[0]	503	1			T14	20		T35	22		T209	26
auto[0]	values[7]	values[1]	588	1			T14	20		T36	57		T186	40
auto[0]	values[7]	values[2]	364	1			T81	20		T166	19		T84	25
auto[0]	values[7]	values[3]	375	1			T9	6		T44	6		T256	4
auto[0]	values[7]	values[4]	342	1			T132	22		T294	10		T225	18
auto[0]	values[7]	values[5]	298	1			T95	26		T31	20		T35	20
auto[0]	values[7]	values[6]	546	1			T30	102		T226	18		T33	18
auto[0]	values[7]	values[7]	408	1			T1	20		T75	6		T195	20
auto[1]	values[0]	values[0]	2	1			T221	1		T295	1		-	-
auto[1]	values[0]	values[1]	3	1			T183	1		T296	1		T297	1
auto[1]	values[0]	values[2]	5	1			T223	3		T298	1		T299	1
auto[1]	values[0]	values[3]	9	1			T300	2		T140	1		T223	1
auto[1]	values[0]	values[4]	8	1			T194	2		T301	2		T157	3
auto[1]	values[0]	values[5]	6	1			T1	1		T302	4		T303	1
auto[1]	values[0]	values[6]	6	1			T298	2		T304	2		T303	2
auto[1]	values[0]	values[7]	2	1			T230	1		T140	1		-	-
auto[1]	values[1]	values[0]	6	1			T58	1		T296	4		T305	1
auto[1]	values[1]	values[1]	8	1			T208	1		T156	2		T306	3
auto[1]	values[1]	values[2]	12	1			T84	1		T307	2		T188	3
auto[1]	values[1]	values[3]	8	1			T271	1		T221	1		T308	2
auto[1]	values[1]	values[4]	1	1			T296	1		-	-		-	-
auto[1]	values[1]	values[5]	11	1			T35	2		T269	2		T309	4
auto[1]	values[1]	values[6]	9	1			T28	3		T310	2		T311	4
auto[1]	values[1]	values[7]	12	1			T84	1		T312	4		T313	2
auto[1]	values[2]	values[0]	8	1			T33	1		T35	1		T160	1
auto[1]	values[2]	values[1]	2	1			T314	2		-	-		-	-
auto[1]	values[2]	values[2]	4	1			T194	2		T273	1		T315	1
auto[1]	values[2]	values[3]	5	1			T30	1		T183	2		T221	1
auto[1]	values[2]	values[4]	1	1			T22	1		-	-		-	-
auto[1]	values[2]	values[5]	8	1			T36	3		T47	2		T237	2
auto[1]	values[2]	values[6]	4	1			T49	3		T140	1		-	-
auto[1]	values[2]	values[7]	1	1			T164	1		-	-		-	-
auto[1]	values[3]	values[0]	4	1			T139	1		T221	1		T279	1
auto[1]	values[3]	values[1]	5	1			T32	1		T198	3		T140	1
auto[1]	values[3]	values[2]	8	1			T47	1		T152	2		T142	1
auto[1]	values[3]	values[3]	12	1			T14	2		T194	1		T49	3
auto[1]	values[3]	values[4]	4	1			T27	1		T157	1		T316	2
auto[1]	values[3]	values[5]	4	1			T306	1		T317	3		-	-
auto[1]	values[3]	values[6]	9	1			T32	1		T36	1		T300	1
auto[1]	values[3]	values[7]	6	1			T188	1		T318	5		-	-
auto[1]	values[4]	values[0]	4	1			T140	1		T207	2		T279	1
auto[1]	values[4]	values[1]	13	1			T84	5		T221	2		T279	4
auto[1]	values[4]	values[2]	3	1			T1	1		T139	1		T269	1
auto[1]	values[4]	values[3]	9	1			T34	4		T225	2		T305	3
auto[1]	values[4]	values[4]	7	1			T298	4		T269	2		T319	1
auto[1]	values[4]	values[5]	10	1			T36	1		T47	1		T152	4
auto[1]	values[4]	values[6]	5	1			T84	1		T140	2		T217	2
auto[1]	values[4]	values[7]	13	1			T1	1		T32	1		T166	2
auto[1]	values[5]	values[0]	6	1			T208	1		T300	2		T223	1
auto[1]	values[5]	values[1]	9	1			T30	1		T152	1		T211	1
auto[1]	values[5]	values[2]	2	1			T320	1		T295	1		-	-
auto[1]	values[5]	values[3]	6	1			T197	1		T204	1		T158	1
auto[1]	values[5]	values[4]	7	1			T31	1		T219	2		T295	3
auto[1]	values[5]	values[5]	5	1			T182	2		T298	1		T219	1
auto[1]	values[5]	values[6]	3	1			T321	2		T182	1		-	-
auto[1]	values[5]	values[7]	7	1			T36	2		T221	1		T157	3
auto[1]	values[6]	values[0]	1	1			T276	1		-	-		-	-
auto[1]	values[6]	values[1]	9	1			T35	2		T183	1		T156	1
auto[1]	values[6]	values[2]	8	1			T35	2		T243	4		T141	2
auto[1]	values[6]	values[3]	5	1			T140	2		T322	2		T310	1
auto[1]	values[6]	values[4]	10	1			T152	2		T49	3		T300	3
auto[1]	values[6]	values[5]	4	1			T168	4		-	-		-	-
auto[1]	values[6]	values[6]	7	1			T36	1		T47	1		T152	1
auto[1]	values[6]	values[7]	6	1			T140	1		T157	3		T323	2
auto[1]	values[7]	values[0]	4	1			T139	1		T188	1		T283	2
auto[1]	values[7]	values[1]	7	1			T36	1		T140	1		T219	1
auto[1]	values[7]	values[2]	11	1			T166	1		T84	1		T160	2
auto[1]	values[7]	values[3]	3	1			T35	1		T318	2		-	-
auto[1]	values[7]	values[4]	6	1			T225	2		T324	4		-	-
auto[1]	values[7]	values[5]	2	1			T276	2		-	-		-	-
auto[1]	values[7]	values[6]	7	1			T33	2		T279	4		T325	1
auto[1]	values[7]	values[7]	6	1			T152	3		T211	1		T307	2