Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T1

9

T6

1

T8

2

auto[1]

1716

1

T1

5

T8

4

T13

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1826

1

T1

14

T6

1

T14

14

auto[1]

1561

1

T8

6

T13

31

T14

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2712

1

T1

7

T6

1

T8

6

auto[1]

675

1

T1

7

T14

5

T15

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	683	1			T1	2		T6	1		T8	1
valid[1]	664	1			T1	5		T8	1		T13	9
valid[2]	653	1			T1	3		T8	2		T13	5
valid[3]	694	1			T1	1		T8	2		T13	4
valid[4]	693	1			T1	3		T13	5		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T1	1		T6	1		T14	2
auto[0]	auto[0]	valid[0]	auto[1]	158	1			T13	4		T17	1		T45	6
auto[0]	auto[0]	valid[1]	auto[0]	99	1			T1	2		T14	1		T18	1
auto[0]	auto[0]	valid[1]	auto[1]	164	1			T13	8		T45	2		T89	1
auto[0]	auto[0]	valid[2]	auto[0]	113	1			T1	1		T14	1		T21	2
auto[0]	auto[0]	valid[2]	auto[1]	140	1			T8	1		T13	5		T17	2
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T14	1		T21	2		T46	1
auto[0]	auto[0]	valid[3]	auto[1]	177	1			T8	1		T13	4		T17	2
auto[0]	auto[0]	valid[4]	auto[0]	114	1			T29	1		T21	1		T59	1
auto[0]	auto[0]	valid[4]	auto[1]	148	1			T13	1		T17	3		T45	2
auto[0]	auto[1]	valid[0]	auto[0]	140	1			T18	1		T29	1		T21	1
auto[0]	auto[1]	valid[0]	auto[1]	158	1			T8	1		T13	4		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T1	1		T15	1		T46	1
auto[0]	auto[1]	valid[1]	auto[1]	157	1			T8	1		T13	1		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	112	1			T1	1		T14	2		T29	2
auto[0]	auto[1]	valid[2]	auto[1]	150	1			T8	1		T17	1		T45	3
auto[0]	auto[1]	valid[3]	auto[0]	117	1			T14	1		T21	2		T46	1
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T8	1		T14	1		T17	1
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T1	1		T14	1		T21	2
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T13	4		T45	5		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	47	1			T14	1		T46	1		T59	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T1	1		T14	1		T15	1
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T1	1		T15	1		T21	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T1	1		T21	3		T170	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T1	2		T46	1		T336	2
auto[1]	auto[1]	valid[0]	auto[0]	60	1			T1	1		T14	1		T28	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T1	1		T59	1		T336	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T31	1		T59	1		T336	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T18	1		T32	2		T35	1
auto[1]	auto[1]	valid[4]	auto[0]	76	1			T14	2		T21	1		T31	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal