Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48098

1

T1

491

T6

4

T14

313

auto[1]

17123

1

T8

6

T13

400

T14

60

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47850

1

T1

319

T6

4

T8

6

auto[1]

17371

1

T1

172

T14

141

T15

7

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33472	1			T1	255		T8	6		T13	206
others[1]	5611	1			T1	44		T6	1		T13	28
others[2]	5382	1			T1	37		T6	1		T13	32
others[3]	6315	1			T1	50		T13	39		T14	39
interest[1]	3776	1			T1	33		T13	15		T14	15
interest[4]	21842	1			T1	162		T8	6		T13	138
interest[64]	10665	1			T1	72		T6	2		T13	80

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15725	1			T1	170		T14	92		T15	7
auto[0]	auto[0]	others[1]	2666	1			T1	31		T6	1		T14	18
auto[0]	auto[0]	others[2]	2582	1			T1	18		T6	1		T14	15
auto[0]	auto[0]	others[3]	2908	1			T1	35		T14	16		T18	18
auto[0]	auto[0]	interest[1]	1857	1			T1	20		T14	7		T16	1
auto[0]	auto[0]	interest[4]	10155	1			T1	109		T14	59		T15	4
auto[0]	auto[0]	interest[64]	4989	1			T1	45		T6	2		T14	24
auto[0]	auto[1]	others[0]	8939	1			T8	6		T13	206		T14	31
auto[0]	auto[1]	others[1]	1457	1			T13	28		T14	10		T45	36
auto[0]	auto[1]	others[2]	1377	1			T13	32		T14	4		T45	31
auto[0]	auto[1]	others[3]	1672	1			T13	39		T14	6		T15	1
auto[0]	auto[1]	interest[1]	918	1			T13	15		T14	2		T45	29
auto[0]	auto[1]	interest[4]	5918	1			T8	6		T13	138		T14	21
auto[0]	auto[1]	interest[64]	2760	1			T13	80		T14	7		T15	1
auto[1]	auto[0]	others[0]	8808	1			T1	85		T14	60		T15	5
auto[1]	auto[0]	others[1]	1488	1			T1	13		T14	19		T18	8
auto[1]	auto[0]	others[2]	1423	1			T1	19		T14	17		T16	1
auto[1]	auto[0]	others[3]	1735	1			T1	15		T14	17		T18	11
auto[1]	auto[0]	interest[1]	1001	1			T1	13		T14	6		T18	9
auto[1]	auto[0]	interest[4]	5769	1			T1	53		T14	41		T15	5
auto[1]	auto[0]	interest[64]	2916	1			T1	27		T14	22		T15	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal