Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	751	1			T59	11		T56	11		T67	25
all_values[1]	751	1			T59	11		T56	11		T67	25
all_values[2]	751	1			T59	11		T56	11		T67	25
all_values[3]	751	1			T59	11		T56	11		T67	25
all_values[4]	751	1			T59	11		T56	11		T67	25
all_values[5]	751	1			T59	11		T56	11		T67	25
all_values[6]	751	1			T59	11		T56	11		T67	25
all_values[7]	751	1			T59	11		T56	11		T67	25

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244

1

T59

39

T56

41

T67

104

auto[1]

2764

1

T59

49

T56

47

T67

96

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410

1

T59

41

T56

41

T67

63

auto[1]

3598

1

T59

47

T56

47

T67

137

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3441

1

T59

55

T56

51

T67

103

auto[1]

2567

1

T59

33

T56

37

T67

97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	152	1			T59	1		T56	1		T67	5
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T59	1		T67	2		T68	1
all_values[0]	auto[0]	auto[1]	auto[0]	144	1			T59	1		T56	3		T67	9
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T59	3		T56	2		T67	1
all_values[0]	auto[1]	auto[0]	auto[1]	154	1			T59	4		T56	2		T67	3
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T59	1		T56	3		T67	5
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T59	5		T56	1		T67	1
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T59	1		T56	1		T67	3
all_values[1]	auto[0]	auto[1]	auto[0]	140	1			T56	4		T67	2		T68	2
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T67	6		T68	2		T164	1
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T59	5		T56	2		T67	6
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T56	3		T67	7		T68	1
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T59	1		T56	1		T67	2
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T67	4		T68	1		T164	2
all_values[2]	auto[0]	auto[1]	auto[0]	113	1			T59	1		T56	3		T67	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T59	2		T56	2		T67	5
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T59	2		T56	2		T67	11
all_values[2]	auto[1]	auto[1]	auto[1]	144	1			T59	5		T56	3		T67	2
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T59	2		T56	1		T67	3
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T59	2		T56	2		T67	4
all_values[3]	auto[0]	auto[1]	auto[0]	133	1			T59	4		T56	3		T67	3
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T56	1		T67	3		T165	2
all_values[3]	auto[1]	auto[0]	auto[1]	196	1			T56	2		T67	7		T68	3
all_values[3]	auto[1]	auto[1]	auto[1]	128	1			T59	3		T56	2		T67	5
all_values[4]	auto[0]	auto[0]	auto[0]	150	1			T56	9		T67	3		T68	2
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T59	2		T67	2		T68	1
all_values[4]	auto[0]	auto[1]	auto[0]	115	1			T59	3		T56	1		T67	5
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T59	1		T67	2		T68	2
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T59	2		T56	1		T67	8
all_values[4]	auto[1]	auto[1]	auto[1]	152	1			T59	3		T67	5		T68	1
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T59	3		T56	3		T67	8
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T59	6		T56	2		T67	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T59	1		T56	1		T67	9
all_values[5]	auto[1]	auto[1]	auto[1]	136	1			T59	1		T56	5		T67	5
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T59	2		T56	3		T67	5
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T56	1		T67	1		T153	2
all_values[6]	auto[0]	auto[1]	auto[0]	133	1			T59	5		T56	2		T67	8
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T59	1		T67	1		T68	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T59	1		T56	1		T67	7
all_values[6]	auto[1]	auto[1]	auto[1]	125	1			T59	2		T56	4		T67	3
all_values[7]	auto[0]	auto[0]	auto[0]	145	1			T59	2		T56	2		T67	2
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T59	1		T56	1		T67	5
all_values[7]	auto[0]	auto[1]	auto[0]	127	1			T59	5		T56	2		T67	3
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T67	1		T68	2		T153	2
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T59	1		T56	4		T67	3
all_values[7]	auto[1]	auto[1]	auto[1]	141	1			T59	2		T56	2		T67	11

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal