Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2445020	1			T1	21		T2	1		T4	1
all_values[1]	2445020	1			T1	21		T2	1		T4	1
all_values[2]	2445020	1			T1	21		T2	1		T4	1
all_values[3]	2445020	1			T1	21		T2	1		T4	1
all_values[4]	2445020	1			T1	21		T2	1		T4	1
all_values[5]	2445020	1			T1	21		T2	1		T4	1
all_values[6]	2445020	1			T1	21		T2	1		T4	1
all_values[7]	2445020	1			T1	21		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19168014

1

T1

168

T2

8

T4

8

auto[1]

392146

1

T12

25079

T34

22

T39

119692

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19537667

1

T1

168

T2

8

T4

8

auto[1]

22493

1

T11

871

T12

90

T47

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2372621	1			T1	21		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	10781	1			T11	500		T12	18		T34	73
all_values[0]	auto[1]	auto[0]	60702	1			T12	4971		T34	6		T39	3
all_values[0]	auto[1]	auto[1]	916	1			T12	41		T34	1		T39	2
all_values[1]	auto[0]	auto[0]	2388255	1			T1	21		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	5824	1			T11	274		T12	6		T34	39
all_values[1]	auto[1]	auto[0]	50516	1			T12	2		T34	2		T39	29887
all_values[1]	auto[1]	auto[1]	425	1			T34	2		T39	32		T63	7
all_values[2]	auto[0]	auto[0]	2375373	1			T1	21		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	1925	1			T11	97		T12	1		T34	38
all_values[2]	auto[1]	auto[0]	67271	1			T12	5012		T34	1		T39	1
all_values[2]	auto[1]	auto[1]	451	1			T12	2		T34	1		T39	1
all_values[3]	auto[0]	auto[0]	2401878	1			T1	21		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	222	1			T12	2		T34	1		T39	1
all_values[3]	auto[1]	auto[0]	42727	1			T12	5012		T34	1		T39	3
all_values[3]	auto[1]	auto[1]	193	1			T12	3		T34	1		T63	8
all_values[4]	auto[0]	auto[0]	2397796	1			T1	21		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	210	1			T12	2		T34	1		T63	2
all_values[4]	auto[1]	auto[0]	46801	1			T12	5011		T34	1		T39	29919
all_values[4]	auto[1]	auto[1]	213	1			T12	3		T34	1		T39	2
all_values[5]	auto[0]	auto[0]	2402713	1			T1	21		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	291	1			T12	1		T47	3		T34	2
all_values[5]	auto[1]	auto[0]	41818	1			T12	3		T34	1		T39	29916
all_values[5]	auto[1]	auto[1]	198	1			T12	1		T34	1		T39	4
all_values[6]	auto[0]	auto[0]	2418790	1			T1	21		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	232	1			T12	2		T39	6		T63	3
all_values[6]	auto[1]	auto[0]	25783	1			T12	5010		T34	1		T63	6
all_values[6]	auto[1]	auto[1]	215	1			T12	5		T39	4		T63	4
all_values[7]	auto[0]	auto[0]	2390914	1			T1	21		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	189	1			T12	1		T34	1		T39	2
all_values[7]	auto[1]	auto[0]	53709	1			T12	1		T34	2		T39	29914
all_values[7]	auto[1]	auto[1]	208	1			T12	2		T39	4		T63	3