Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	27096	1			T1	43		T2	2		T9	4
auto[SpiFlashAddrCfg]	5828	1			T1	4		T2	6		T11	100
auto[SpiFlashAddr3b]	7249	1			T1	2		T2	6		T9	6
auto[SpiFlashAddr4b]	5867	1			T2	2		T9	6		T10	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26799

1

T1

49

T2

16

T9

16

auto[1]

19241

1

T10

2

T11

228

T12

325

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24971

1

T1

8

T2

8

T9

10

auto[1]

21069

1

T1

41

T2

8

T9

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	30745	1			T1	47		T2	2		T9	4
values[1]	866	1			T11	16		T12	5		T13	10
values[2]	1119	1			T9	6		T11	13		T12	16
values[3]	1167	1			T1	2		T9	4		T11	14
values[4]	1119	1			T11	24		T12	15		T13	10
values[5]	1130	1			T2	2		T9	2		T11	12
values[6]	1159	1			T2	2		T11	17		T12	15
values[7]	1166	1			T2	4		T11	20		T12	23
values[8]	7569	1			T2	6		T10	2		T11	128

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25409

1

T1

49

T2

16

T9

16

auto[1]

20631

1

T11

400

T13

265

T22

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

44358

1

T1

49

T2

16

T9

16

write

1682

1

T11

43

T12

32

T13

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15494

1

T1

8

T2

12

T9

12

valids[0x1]

30546

1

T1

41

T2

4

T9

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1213	1			T1	2		T11	19		T12	18
internal_process_ops[0x5a]	1245	1			T2	2		T11	31		T12	23
internal_process_ops[0x05]	16250	1			T1	37		T11	127		T12	275
internal_process_ops[0x35]	1181	1			T9	4		T11	13		T12	24
internal_process_ops[0x15]	1253	1			T2	2		T11	17		T12	14
internal_process_ops[0x03]	917	1			T11	13		T12	9		T13	1
internal_process_ops[0x0b]	858	1			T11	9		T12	26		T13	2
internal_process_ops[0x3b]	870	1			T11	12		T12	28		T13	1
internal_process_ops[0x6b]	921	1			T2	4		T9	6		T11	10
internal_process_ops[0xbb]	864	1			T2	2		T9	2		T11	12
internal_process_ops[0xeb]	828	1			T1	2		T9	4		T11	15

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45194

1

T1

49

T2

16

T9

16

auto[1]

846

1

T11

33

T12

13

T13

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44441

1

T1

47

T2

16

T9

16

auto[1]

1599

1

T1

2

T11

43

T12

26

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9086

1

T1

43

T2

2

T9

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4605

1

T11

22

T12

156

T32

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1652

1

T1

4

T2

6

T11

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1606

1

T11

16

T12

39

T32

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2282

1

T1

2

T2

6

T9

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1903

1

T11

22

T12

61

T32

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1801

1

T2

2

T9

6

T11

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1553

1

T10

2

T11

18

T12

49

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

58

1

T32

1

T33

1

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

50

1

T12

2

T35

1

T49

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

58

1

T11

1

T12

1

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

57

1

T12

1

T33

1

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

69

1

T12

2

T33

3

T49

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

36

1

T11

1

T38

1

T39

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

45

1

T12

7

T39

1

T165

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

65

1

T11

3

T12

3

T166

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

50

1

T39

2

T79

1

T167

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T12

1

T33

3

T39

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

57

1

T12

1

T35

1

T111

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T11

1

T12

4

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

70

1

T12

6

T49

1

T38

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

40

1

T12

1

T33

3

T166

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T12

2

T33

6

T38

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

66

1

T11

1

T12

1

T38

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7634

1

T11

138

T13

73

T31

11

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5345

1

T11

44

T13

65

T31

49

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1147

1

T11

33

T13

15

T22

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1005

1

T11

26

T13

15

T31

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1319

1

T11

43

T13

20

T31

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1313

1

T11

32

T13

26

T31

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1057

1

T11

23

T13

25

T31

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1050

1

T11

25

T13

20

T31

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

52

1

T13

1

T31

1

T29

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

42

1

T11

2

T29

2

T168

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

50

1

T11

4

T29

2

T34

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T11

4

T34

2

T63

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

59

1

T13

2

T168

1

T169

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T11

8

T34

1

T168

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

42

1

T13

1

T23

3

T24

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

48

1

T23

3

T133

1

T170

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

42

1

T11

3

T13

1

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

54

1

T11

3

T48

1

T168

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

36

1

T11

2

T131

1

T171

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

52

1

T11

3

T29

3

T172

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

46

1

T29

2

T173

1

T172

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

44

1

T11

3

T13

1

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

43

1

T48

2

T168

2

T172

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

38

1

T11

4

T174

1

T175

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3484	1			T1	6		T11	36		T12	90
auto[0]	values[0]	valids[0x1]	12458	1			T1	41		T2	2		T9	4
auto[0]	values[1]	valids[0x1]	519	1			T11	6		T12	5		T32	2
auto[0]	values[2]	valids[0x0]	434	1			T9	6		T11	2		T12	8
auto[0]	values[2]	valids[0x1]	261	1			T11	4		T12	8		T33	13
auto[0]	values[3]	valids[0x0]	493	1			T1	2		T9	4		T11	7
auto[0]	values[3]	valids[0x1]	260	1			T11	1		T12	5		T33	2
auto[0]	values[4]	valids[0x0]	445	1			T11	7		T12	14		T33	9
auto[0]	values[4]	valids[0x1]	232	1			T11	1		T12	1		T33	5
auto[0]	values[5]	valids[0x0]	475	1			T2	2		T9	2		T11	2
auto[0]	values[5]	valids[0x1]	209	1			T11	3		T12	9		T33	2
auto[0]	values[6]	valids[0x0]	453	1			T11	5		T12	7		T33	7
auto[0]	values[6]	valids[0x1]	253	1			T2	2		T11	4		T12	8
auto[0]	values[7]	valids[0x0]	474	1			T2	4		T11	6		T12	17
auto[0]	values[7]	valids[0x1]	285	1			T11	3		T12	6		T33	2
auto[0]	values[8]	valids[0x0]	2966	1			T2	6		T10	2		T11	25
auto[0]	values[8]	valids[0x1]	1708	1			T11	23		T12	29		T32	2
auto[1]	values[0]	valids[0x0]	2982	1			T11	75		T13	48		T31	11
auto[1]	values[0]	valids[0x1]	11821	1			T11	180		T13	100		T22	1
auto[1]	values[1]	valids[0x1]	347	1			T11	10		T13	10		T31	3
auto[1]	values[2]	valids[0x0]	278	1			T11	5		T13	6		T29	1
auto[1]	values[2]	valids[0x1]	146	1			T11	2		T13	5		T31	2
auto[1]	values[3]	valids[0x0]	264	1			T11	6		T13	8		T31	1
auto[1]	values[3]	valids[0x1]	150	1			T13	8		T48	1		T168	2
auto[1]	values[4]	valids[0x0]	255	1			T11	9		T13	3		T29	3
auto[1]	values[4]	valids[0x1]	187	1			T11	7		T13	7		T29	2
auto[1]	values[5]	valids[0x0]	276	1			T11	7		T13	3		T29	6
auto[1]	values[5]	valids[0x1]	170	1			T13	2		T29	3		T34	1
auto[1]	values[6]	valids[0x0]	269	1			T11	6		T13	3		T31	2
auto[1]	values[6]	valids[0x1]	184	1			T11	2		T13	3		T31	2
auto[1]	values[7]	valids[0x0]	267	1			T11	9		T13	2		T29	1
auto[1]	values[7]	valids[0x1]	140	1			T11	2		T13	6		T31	3
auto[1]	values[8]	valids[0x0]	1679	1			T11	53		T13	29		T31	4
auto[1]	values[8]	valids[0x1]	1216	1			T11	27		T13	22		T31	3