Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2740551

1

T1

5

T2

1

T7

1

auto[1]

15008

1

T1

37

T11

114

T12

258

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844157

1

T1

5

T2

1

T7

1

auto[1]

1911402

1

T1

37

T11

18186

T12

45337

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	513191	1			T1	42		T2	1		T7	1
auto[524288:1048575]	337076	1			T9	420		T11	3119		T12	6455
auto[1048576:1572863]	291486	1			T9	82		T11	3261		T12	2879
auto[1572864:2097151]	351907	1			T9	23		T11	1408		T12	6595
auto[2097152:2621439]	370614	1			T9	15		T11	17		T12	6025
auto[2621440:3145727]	305110	1			T9	820		T11	4381		T12	4764
auto[3145728:3670015]	285884	1			T9	410		T11	760		T12	7231
auto[3670016:4194303]	300291	1			T9	787		T11	4897		T12	3602

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929199

1

T1

41

T2

1

T7

1

auto[1]

826360

1

T1

1

T9

2930

T11

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2398896

1

T1

42

T2

1

T7

1

auto[1]

356663

1

T11

3387

T12

6412

T13

736

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	173902	1			T1	3		T2	1		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	299623	1			T1	2		T11	260		T12	5669
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	86203	1			T9	420		T11	23		T12	16
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	207748	1			T11	3086		T12	6340		T13	610
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	81177	1			T9	82		T11	21		T12	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	162546	1			T11	902		T12	2868		T13	66
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	111884	1			T9	23		T11	19		T12	14
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	177915	1			T11	949		T12	6580		T13	3472
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	106785	1			T9	15		T11	7		T12	17
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	217569	1			T11	3		T12	5983		T13	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	92873	1			T9	820		T11	21		T12	20
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	170678	1			T11	4347		T12	4671		T13	514
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	94727	1			T9	410		T11	8		T12	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	141507	1			T11	535		T12	3556		T13	430
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	89022	1			T9	787		T11	10		T12	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	172752	1			T11	4716		T12	3074		T13	816
auto[0]	auto[1]	auto[0:524287]	auto[0]	1191	1			T11	5		T12	8		T13	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	36143	1			T11	260		T12	2190		T33	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1101	1			T12	2		T13	4		T29	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39872	1			T13	257		T29	2408		T49	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	828	1			T11	13		T12	2		T32	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45235	1			T11	2308		T12	1		T48	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	242	1			T11	7		T12	1		T13	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	60028	1			T11	394		T13	129		T29	1379
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	198	1			T11	2		T12	2		T168	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44361	1			T12	1		T33	512		T39	2800
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	283	1			T11	5		T12	2		T31	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39805	1			T12	1		T31	1		T34	1246
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	736	1			T11	6		T12	2		T13	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47034	1			T11	201		T12	3659		T13	332
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1400	1			T11	6		T29	3		T33	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	35183	1			T11	154		T12	512		T33	2771
auto[1]	auto[0]	auto[0:524287]	auto[0]	212	1			T1	2		T11	4		T12	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	1737	1			T1	35		T11	6		T12	30
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	157	1			T11	6		T12	5		T29	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1622	1			T11	4		T12	92		T29	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	141	1			T11	6		T13	1		T29	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1049	1			T11	1		T13	24		T29	30
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	153	1			T11	5		T13	1		T29	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1322	1			T11	34		T13	1		T29	118
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	183	1			T11	3		T12	3		T31	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1384	1			T11	2		T12	18		T31	35
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	142	1			T11	5		T12	6		T13	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1026	1			T11	3		T12	64		T13	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	143	1			T11	2		T29	1		T33	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1312	1			T29	2		T33	123		T38	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	163	1			T11	2		T12	2		T13	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1239	1			T11	5		T12	4		T13	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	40	1			T11	2		T12	2		T33	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	343	1			T11	2		T12	23		T33	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	32	1			T13	1		T39	1		T40	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	341	1			T13	1		T40	51		T124	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	52	1			T11	4		T12	1		T48	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	458	1			T11	6		T48	6		T40	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	40	1			T13	1		T29	1		T39	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	323	1			T13	1		T29	10		T39	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	25	1			T12	1		T40	1		T169	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	109	1			T40	1		T169	14		T170	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	37	1			T31	1		T48	1		T24	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	266	1			T31	4		T48	6		T173	22
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	46	1			T11	3		T12	1		T33	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	379	1			T11	5		T12	1		T33	19
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	39	1			T11	1		T38	1		T39	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	493	1			T11	3		T24	1		T133	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1565021	1			T1	4		T2	1		T7	1
auto[0]	auto[0]	auto[1]	821890	1			T1	1		T9	2930		T11	1
auto[0]	auto[1]	auto[0]	349425	1			T11	3361		T12	6382		T13	732
auto[0]	auto[1]	auto[1]	4215	1			T12	1		T191	3		T169	1
auto[1]	auto[0]	auto[0]	11775	1			T1	37		T11	86		T12	221
auto[1]	auto[0]	auto[1]	210	1			T11	2		T12	8		T13	5
auto[1]	auto[1]	auto[0]	2978	1			T11	26		T12	27		T13	3
auto[1]	auto[1]	auto[1]	45	1			T12	2		T13	1		T40	1