Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15249

1

T1

49

T2

16

T9

16

auto[1]

10160

1

T10

2

T11

84

T12

325

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2989	1			T11	40		T12	130		T90	6
values[1]	2807	1			T2	16		T11	25		T12	90
values[2]	3223	1			T1	49		T11	46		T12	248
values[3]	3887	1			T11	25		T12	85		T98	2
values[4]	2976	1			T12	56		T32	29		T33	20
values[5]	3097	1			T11	29		T12	85		T33	245
values[6]	2746	1			T10	2		T12	20		T33	62
values[7]	3684	1			T9	16		T11	69		T12	44

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2815	1			T12	20		T176	6		T33	103
values[1]	2659	1			T12	42		T35	20		T190	24
values[2]	2765	1			T12	91		T33	20		T210	22
values[3]	3429	1			T1	49		T2	16		T11	20
values[4]	3955	1			T9	16		T11	100		T12	159
values[5]	2953	1			T11	23		T12	255		T17	2
values[6]	2950	1			T10	2		T12	40		T98	2
values[7]	3883	1			T11	91		T12	45		T33	107

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	201	1			T216	15		T249	35		T242	10
auto[0]	values[0]	values[1]	108	1			T12	12		T35	15		T198	12
auto[0]	values[0]	values[2]	226	1			T39	10		T80	14		T70	6
auto[0]	values[0]	values[3]	234	1			T11	12		T12	5		T33	10
auto[0]	values[0]	values[4]	271	1			T90	6		T39	18		T40	22
auto[0]	values[0]	values[5]	154	1			T12	67		T33	42		T264	9
auto[0]	values[0]	values[6]	200	1			T35	12		T167	13		T80	10
auto[0]	values[0]	values[7]	365	1			T11	14		T166	34		T188	24
auto[0]	values[1]	values[0]	249	1			T38	43		T198	13		T225	37
auto[0]	values[1]	values[1]	167	1			T190	24		T49	10		T79	22
auto[0]	values[1]	values[2]	204	1			T12	39		T49	21		T167	17
auto[0]	values[1]	values[3]	182	1			T2	16		T33	15		T49	10
auto[0]	values[1]	values[4]	172	1			T12	11		T24	10		T238	33
auto[0]	values[1]	values[5]	246	1			T12	13		T17	2		T290	12
auto[0]	values[1]	values[6]	158	1			T39	19		T167	13		T291	10
auto[0]	values[1]	values[7]	232	1			T11	15		T132	10		T80	6
auto[0]	values[2]	values[0]	239	1			T12	6		T278	22		T198	24
auto[0]	values[2]	values[1]	176	1			T212	10		T70	8		T292	18
auto[0]	values[2]	values[2]	206	1			T12	9		T39	11		T40	17
auto[0]	values[2]	values[3]	339	1			T1	49		T111	12		T166	4
auto[0]	values[2]	values[4]	315	1			T12	76		T33	23		T181	10
auto[0]	values[2]	values[5]	173	1			T12	11		T124	17		T24	12
auto[0]	values[2]	values[6]	141	1			T12	19		T111	15		T181	6
auto[0]	values[2]	values[7]	325	1			T11	20		T49	20		T39	12
auto[0]	values[3]	values[0]	298	1			T33	12		T38	24		T40	30
auto[0]	values[3]	values[1]	414	1			T293	2		T249	52		T213	12
auto[0]	values[3]	values[2]	364	1			T12	12		T210	22		T38	13
auto[0]	values[3]	values[3]	348	1			T12	45		T220	24		T206	28
auto[0]	values[3]	values[4]	212	1			T11	18		T80	13		T282	24
auto[0]	values[3]	values[5]	366	1			T39	82		T167	14		T80	15
auto[0]	values[3]	values[6]	249	1			T98	2		T201	7		T80	8
auto[0]	values[3]	values[7]	189	1			T49	13		T38	9		T167	11
auto[0]	values[4]	values[0]	207	1			T197	13		T249	14		T243	12
auto[0]	values[4]	values[1]	235	1			T166	8		T192	2		T80	16
auto[0]	values[4]	values[2]	196	1			T39	19		T294	4		T230	12
auto[0]	values[4]	values[3]	287	1			T39	33		T166	16		T24	13
auto[0]	values[4]	values[4]	295	1			T12	10		T32	6		T33	12
auto[0]	values[4]	values[5]	140	1			T111	12		T181	9		T24	18
auto[0]	values[4]	values[6]	204	1			T49	12		T40	7		T165	12
auto[0]	values[4]	values[7]	263	1			T49	12		T40	105		T185	11
auto[0]	values[5]	values[0]	331	1			T99	8		T80	26		T295	8
auto[0]	values[5]	values[1]	86	1			T12	8		T211	4		T80	21
auto[0]	values[5]	values[2]	194	1			T191	22		T198	16		T197	11
auto[0]	values[5]	values[3]	181	1			T33	12		T177	18		T80	11
auto[0]	values[5]	values[4]	367	1			T11	22		T33	81		T38	11
auto[0]	values[5]	values[5]	168	1			T12	13		T124	18		T167	19
auto[0]	values[5]	values[6]	198	1			T184	20		T178	51		T296	8
auto[0]	values[5]	values[7]	216	1			T12	39		T194	2		T297	12
auto[0]	values[6]	values[0]	196	1			T70	10		T298	24		T243	11
auto[0]	values[6]	values[1]	240	1			T124	20		T217	10		T80	49
auto[0]	values[6]	values[2]	161	1			T109	10		T40	14		T80	11
auto[0]	values[6]	values[3]	196	1			T33	12		T167	18		T299	20
auto[0]	values[6]	values[4]	251	1			T38	13		T214	9		T80	13
auto[0]	values[6]	values[5]	111	1			T12	13		T167	13		T70	8
auto[0]	values[6]	values[6]	164	1			T38	53		T111	11		T124	14
auto[0]	values[6]	values[7]	316	1			T80	10		T70	16		T238	15
auto[0]	values[7]	values[0]	153	1			T176	6		T33	8		T40	11
auto[0]	values[7]	values[1]	281	1			T39	8		T124	12		T167	17
auto[0]	values[7]	values[2]	296	1			T33	9		T80	45		T216	18
auto[0]	values[7]	values[3]	258	1			T12	13		T39	13		T80	17
auto[0]	values[7]	values[4]	491	1			T9	16		T11	38		T38	22
auto[0]	values[7]	values[5]	333	1			T11	11		T12	12		T80	55
auto[0]	values[7]	values[6]	202	1			T111	16		T300	4		T24	14
auto[0]	values[7]	values[7]	309	1			T33	87		T39	10		T40	15
auto[1]	values[0]	values[0]	107	1			T216	5		T249	21		T242	10
auto[1]	values[0]	values[1]	103	1			T12	10		T35	5		T110	6
auto[1]	values[0]	values[2]	140	1			T39	10		T80	6		T70	14
auto[1]	values[0]	values[3]	158	1			T11	8		T12	15		T33	10
auto[1]	values[0]	values[4]	199	1			T39	23		T40	23		T214	7
auto[1]	values[0]	values[5]	90	1			T12	21		T33	8		T264	42
auto[1]	values[0]	values[6]	112	1			T35	13		T167	7		T80	10
auto[1]	values[0]	values[7]	321	1			T11	6		T166	12		T165	63
auto[1]	values[1]	values[0]	106	1			T38	8		T198	7		T225	9
auto[1]	values[1]	values[1]	66	1			T49	11		T79	7		T111	6
auto[1]	values[1]	values[2]	110	1			T12	11		T49	5		T167	10
auto[1]	values[1]	values[3]	135	1			T33	22		T49	11		T166	5
auto[1]	values[1]	values[4]	145	1			T12	9		T24	10		T238	10
auto[1]	values[1]	values[5]	195	1			T12	7		T24	20		T165	8
auto[1]	values[1]	values[6]	324	1			T39	50		T167	15		T288	18
auto[1]	values[1]	values[7]	116	1			T11	10		T80	17		T223	20
auto[1]	values[2]	values[0]	164	1			T12	14		T198	6		T246	6
auto[1]	values[2]	values[1]	66	1			T70	12		T301	2		T231	8
auto[1]	values[2]	values[2]	86	1			T12	11		T39	9		T40	3
auto[1]	values[2]	values[3]	252	1			T111	9		T166	37		T185	7
auto[1]	values[2]	values[4]	154	1			T12	7		T33	45		T181	10
auto[1]	values[2]	values[5]	238	1			T12	74		T124	16		T24	10
auto[1]	values[2]	values[6]	111	1			T12	21		T111	7		T181	14
auto[1]	values[2]	values[7]	238	1			T11	26		T49	4		T39	8
auto[1]	values[3]	values[0]	126	1			T33	8		T38	9		T40	13
auto[1]	values[3]	values[1]	181	1			T249	4		T213	15		T178	41
auto[1]	values[3]	values[2]	130	1			T12	9		T38	17		T80	9
auto[1]	values[3]	values[3]	165	1			T12	19		T189	2		T185	12
auto[1]	values[3]	values[4]	124	1			T11	7		T80	18		T246	10
auto[1]	values[3]	values[5]	206	1			T39	10		T167	10		T80	5
auto[1]	values[3]	values[6]	214	1			T201	20		T80	26		T70	13
auto[1]	values[3]	values[7]	301	1			T49	14		T38	11		T167	9
auto[1]	values[4]	values[0]	121	1			T197	7		T249	6		T243	8
auto[1]	values[4]	values[1]	148	1			T166	14		T302	12		T80	4
auto[1]	values[4]	values[2]	47	1			T39	5		T230	8		T54	5
auto[1]	values[4]	values[3]	123	1			T39	4		T166	8		T24	9
auto[1]	values[4]	values[4]	201	1			T12	46		T32	23		T33	8
auto[1]	values[4]	values[5]	138	1			T111	8		T181	20		T24	35
auto[1]	values[4]	values[6]	249	1			T49	8		T40	49		T259	16
auto[1]	values[4]	values[7]	122	1			T49	8		T40	6		T185	9
auto[1]	values[5]	values[0]	89	1			T80	6		T236	5		T250	10
auto[1]	values[5]	values[1]	83	1			T12	12		T41	10		T80	11
auto[1]	values[5]	values[2]	109	1			T198	12		T197	9		T199	9
auto[1]	values[5]	values[3]	210	1			T33	145		T80	9		T225	10
auto[1]	values[5]	values[4]	295	1			T11	7		T33	7		T38	9
auto[1]	values[5]	values[5]	138	1			T12	7		T124	5		T167	8
auto[1]	values[5]	values[6]	174	1			T178	43		T225	9		T51	11
auto[1]	values[5]	values[7]	258	1			T12	6		T198	4		T243	47
auto[1]	values[6]	values[0]	82	1			T70	10		T303	10		T243	9
auto[1]	values[6]	values[1]	171	1			T124	6		T80	62		T199	9
auto[1]	values[6]	values[2]	118	1			T40	6		T42	22		T80	9
auto[1]	values[6]	values[3]	157	1			T33	50		T167	6		T70	9
auto[1]	values[6]	values[4]	206	1			T38	13		T214	53		T80	7
auto[1]	values[6]	values[5]	130	1			T12	7		T195	14		T167	7
auto[1]	values[6]	values[6]	103	1			T10	2		T38	11		T111	9
auto[1]	values[6]	values[7]	144	1			T80	10		T70	4		T238	10
auto[1]	values[7]	values[0]	146	1			T33	75		T40	9		T165	9
auto[1]	values[7]	values[1]	134	1			T39	12		T202	6		T124	8
auto[1]	values[7]	values[2]	178	1			T33	11		T80	22		T216	2
auto[1]	values[7]	values[3]	204	1			T12	9		T39	9		T304	6
auto[1]	values[7]	values[4]	257	1			T11	8		T38	10		T39	5
auto[1]	values[7]	values[5]	127	1			T11	12		T12	10		T43	20
auto[1]	values[7]	values[6]	147	1			T111	6		T24	10		T167	15
auto[1]	values[7]	values[7]	168	1			T33	20		T39	10		T40	5