Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	350	1			T9	12		T11	2		T12	8
auto[ReadAddrCrossIntoMailbox]	256	1			T11	1		T12	9		T210	8
auto[ReadAddrCrossOutOfMailbox]	271	1			T11	4		T12	7		T33	4
auto[ReadAddrCrossAllMailbox]	205	1			T11	2		T12	4		T33	3
auto[ReadAddrOutsideMailbox]	3060	1			T1	2		T2	6		T11	33

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2014

1

T1

1

T2

3

T9

6

auto[1]

2128

1

T1

1

T2

3

T9

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	709	1			T11	9		T12	9		T33	12
read_ops[0x0b]	690	1			T11	4		T12	26		T33	7
read_ops[0x3b]	686	1			T11	10		T12	28		T90	2
read_ops[0x6b]	724	1			T2	4		T9	6		T11	7
read_ops[0xbb]	682	1			T2	2		T9	2		T11	7
read_ops[0xeb]	651	1			T1	2		T9	4		T11	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T99	1		T39	1		T111	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T33	1		T99	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T49	1		T38	1		T40	4
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T12	1		T49	2		T40	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T11	1		T12	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T12	1		T49	1		T111	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T210	1		T124	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T210	1		T111	1		T204	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T11	7		T12	5		T33	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T11	1		T12	1		T33	10
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T12	1		T35	1		T38	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T12	2		T49	1		T111	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T12	1		T210	4		T39	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T12	4		T210	4		T39	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T210	1		T35	1		T39	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T12	1		T210	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T12	1		T40	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T12	1		T39	1		T111	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T11	2		T12	8		T33	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T11	2		T12	7		T33	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T11	1		T90	1		T99	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T12	2		T90	1		T99	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T39	1		T40	1		T306	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T12	1		T38	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T33	2		T210	1		T201	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T12	2		T33	1		T210	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T11	1		T210	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T210	1		T49	1		T39	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T11	3		T12	8		T33	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T11	5		T12	15		T210	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T9	3		T11	1		T187	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T9	3		T39	1		T187	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T203	1		T204	1		T80	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T12	1		T111	1		T24	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T11	2		T49	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T33	1		T38	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T49	2		T204	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T12	1		T79	1		T204	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T2	2		T11	2		T12	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T2	2		T11	2		T12	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T9	1		T12	2		T40	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T9	1		T12	1		T33	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T11	1		T49	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T39	1		T111	1		T70	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T49	1		T39	2		T79	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T11	1		T35	1		T111	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T11	1		T33	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T40	1		T80	1		T70	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T2	1		T11	1		T12	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T2	1		T11	3		T12	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T9	2		T35	1		T39	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T9	2		T39	1		T184	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T12	1		T39	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T204	1		T80	2		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T12	1		T49	1		T185	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T12	1		T39	1		T246	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T33	1		T166	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	1		T33	1		T80	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	241	1			T1	1		T11	4		T12	8
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	257	1			T1	1		T11	1		T12	4