Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2445020	1			T1	21		T2	1		T4	1
all_pins[1]	2445020	1			T1	21		T2	1		T4	1
all_pins[2]	2445020	1			T1	21		T2	1		T4	1
all_pins[3]	2445020	1			T1	21		T2	1		T4	1
all_pins[4]	2445020	1			T1	21		T2	1		T4	1
all_pins[5]	2445020	1			T1	21		T2	1		T4	1
all_pins[6]	2445020	1			T1	21		T2	1		T4	1
all_pins[7]	2445020	1			T1	21		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19530867	1			T1	168		T2	8		T4	8
values[0x1]	29293	1			T12	5070		T34	7		T39	284
transitions[0x0=>0x1]	28243	1			T12	5066		T34	4		T39	278
transitions[0x1=>0x0]	28255	1			T12	5066		T34	4		T39	278

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2444044	1			T1	21		T2	1		T4	1
all_pins[0]	values[0x1]	976	1			T12	50		T34	1		T39	2
all_pins[0]	transitions[0x0=>0x1]	721	1			T12	50		T39	1		T63	2
all_pins[0]	transitions[0x1=>0x0]	191	1			T34	1		T39	41		T63	4
all_pins[1]	values[0x0]	2444574	1			T1	21		T2	1		T4	1
all_pins[1]	values[0x1]	446	1			T34	2		T39	42		T63	7
all_pins[1]	transitions[0x0=>0x1]	253	1			T34	1		T39	41		T63	6
all_pins[1]	transitions[0x1=>0x0]	271	1			T12	2		T63	1		T126	2
all_pins[2]	values[0x0]	2444556	1			T1	21		T2	1		T4	1
all_pins[2]	values[0x1]	464	1			T12	2		T34	1		T39	1
all_pins[2]	transitions[0x0=>0x1]	406	1			T12	1		T34	1		T39	1
all_pins[2]	transitions[0x1=>0x0]	135	1			T12	2		T34	1		T63	6
all_pins[3]	values[0x0]	2444827	1			T1	21		T2	1		T4	1
all_pins[3]	values[0x1]	193	1			T12	3		T34	1		T63	8
all_pins[3]	transitions[0x0=>0x1]	136	1			T12	2		T34	1		T63	4
all_pins[3]	transitions[0x1=>0x0]	156	1			T12	2		T34	1		T39	2
all_pins[4]	values[0x0]	2444807	1			T1	21		T2	1		T4	1
all_pins[4]	values[0x1]	213	1			T12	3		T34	1		T39	2
all_pins[4]	transitions[0x0=>0x1]	155	1			T12	3		T39	2		T63	3
all_pins[4]	transitions[0x1=>0x0]	1139	1			T12	1		T39	229		T126	2
all_pins[5]	values[0x0]	2443823	1			T1	21		T2	1		T4	1
all_pins[5]	values[0x1]	1197	1			T12	1		T34	1		T39	229
all_pins[5]	transitions[0x0=>0x1]	882	1			T34	1		T39	227		T63	4
all_pins[5]	transitions[0x1=>0x0]	25281	1			T12	5008		T39	2		T63	3
all_pins[6]	values[0x0]	2419424	1			T1	21		T2	1		T4	1
all_pins[6]	values[0x1]	25596	1			T12	5009		T39	4		T63	4
all_pins[6]	transitions[0x0=>0x1]	25539	1			T12	5008		T39	2		T63	3
all_pins[6]	transitions[0x1=>0x0]	151	1			T12	1		T39	2		T63	2
all_pins[7]	values[0x0]	2444812	1			T1	21		T2	1		T4	1
all_pins[7]	values[0x1]	208	1			T12	2		T39	4		T63	3
all_pins[7]	transitions[0x0=>0x1]	151	1			T12	2		T39	4		T63	2
all_pins[7]	transitions[0x1=>0x0]	931	1			T12	50		T34	1		T39	2