Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3126	1			T11	20		T12	168		T17	2
values[1]	2768	1			T9	16		T11	26		T12	41
values[2]	3366	1			T1	49		T10	2		T12	86
values[3]	3048	1			T11	48		T12	128		T49	41
values[4]	3242	1			T11	54		T12	128		T33	260
values[5]	3160	1			T2	16		T12	60		T176	6
values[6]	3381	1			T11	20		T12	40		T98	2
values[7]	3318	1			T11	66		T12	107		T33	88

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3353	1			T11	66		T12	117		T90	6
values[1]	2838	1			T10	2		T12	122		T33	82
values[2]	2974	1			T11	25		T12	22		T32	29
values[3]	3573	1			T11	46		T12	225		T17	2
values[4]	3112	1			T12	148		T98	2		T33	87
values[5]	3614	1			T2	16		T9	16		T11	29
values[6]	2947	1			T1	49		T11	45		T12	22
values[7]	2998	1			T11	23		T12	40		T33	157

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24954

1

T1

49

T2

16

T9

16

auto[1]

455

1

T11

6

T12

13

T32

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[4]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	311	1			T39	21		T40	20		T24	41
auto[0]	values[0]	values[1]	390	1			T33	59		T40	24		T177	18
auto[0]	values[0]	values[2]	173	1			T178	38		T179	20		T180	8
auto[0]	values[0]	values[3]	695	1			T11	19		T12	85		T17	2
auto[0]	values[0]	values[4]	579	1			T12	83		T33	86		T181	26
auto[0]	values[0]	values[5]	310	1			T124	22		T165	20		T182	37
auto[0]	values[0]	values[6]	293	1			T40	68		T124	19		T183	25
auto[0]	values[0]	values[7]	321	1			T43	20		T184	20		T185	28
auto[0]	values[1]	values[0]	235	1			T166	22		T80	40		T186	20
auto[0]	values[1]	values[1]	366	1			T38	25		T187	22		T80	67
auto[0]	values[1]	values[2]	285	1			T32	27		T38	20		T39	26
auto[0]	values[1]	values[3]	174	1			T11	25		T111	21		T188	24
auto[0]	values[1]	values[4]	268	1			T109	10		T189	2		T24	26
auto[0]	values[1]	values[5]	643	1			T9	16		T12	40		T33	20
auto[0]	values[1]	values[6]	460	1			T33	87		T185	20		T80	20
auto[0]	values[1]	values[7]	301	1			T190	24		T38	20		T124	20
auto[0]	values[2]	values[0]	412	1			T12	22		T33	20		T191	22
auto[0]	values[2]	values[1]	365	1			T10	2		T12	19		T80	62
auto[0]	values[2]	values[2]	529	1			T33	20		T192	2		T80	93
auto[0]	values[2]	values[3]	453	1			T12	44		T35	24		T39	20
auto[0]	values[2]	values[4]	302	1			T166	41		T80	43		T193	6
auto[0]	values[2]	values[5]	442	1			T111	22		T194	2		T195	12
auto[0]	values[2]	values[6]	348	1			T1	49		T49	26		T124	32
auto[0]	values[2]	values[7]	461	1			T40	40		T185	20		T70	20
auto[0]	values[3]	values[0]	238	1			T12	48		T196	8		T197	23
auto[0]	values[3]	values[1]	384	1			T39	89		T198	20		T199	24
auto[0]	values[3]	values[2]	319	1			T11	22		T24	46		T80	23
auto[0]	values[3]	values[3]	730	1			T12	53		T39	20		T165	50
auto[0]	values[3]	values[4]	292	1			T38	20		T79	29		T165	74
auto[0]	values[3]	values[5]	289	1			T80	40		T70	20		T200	14
auto[0]	values[3]	values[6]	431	1			T12	22		T49	20		T124	24
auto[0]	values[3]	values[7]	321	1			T11	23		T49	21		T38	33
auto[0]	values[4]	values[0]	399	1			T12	45		T39	21		T166	21
auto[0]	values[4]	values[1]	224	1			T12	21		T33	20		T166	18
auto[0]	values[4]	values[2]	494	1			T111	22		T201	20		T80	32
auto[0]	values[4]	values[3]	446	1			T12	19		T202	6		T111	20
auto[0]	values[4]	values[4]	360	1			T12	20		T166	20		T203	10
auto[0]	values[4]	values[5]	528	1			T11	28		T12	21		T33	83
auto[0]	values[4]	values[6]	371	1			T11	25		T25	23		T165	19
auto[0]	values[4]	values[7]	357	1			T33	155		T204	8		T205	22
auto[0]	values[5]	values[0]	706	1			T49	20		T40	107		T206	28
auto[0]	values[5]	values[1]	265	1			T12	39		T207	10		T197	73
auto[0]	values[5]	values[2]	362	1			T176	6		T39	40		T208	8
auto[0]	values[5]	values[3]	307	1			T132	10		T80	27		T209	4
auto[0]	values[5]	values[4]	393	1			T210	22		T39	19		T211	4
auto[0]	values[5]	values[5]	489	1			T2	16		T33	47		T49	24
auto[0]	values[5]	values[6]	398	1			T40	22		T201	27		T80	20
auto[0]	values[5]	values[7]	173	1			T12	20		T166	22		T40	20
auto[0]	values[6]	values[0]	587	1			T11	20		T90	6		T39	45
auto[0]	values[6]	values[1]	460	1			T12	39		T212	10		T80	31
auto[0]	values[6]	values[2]	322	1			T124	26		T213	26		T178	20
auto[0]	values[6]	values[3]	382	1			T33	20		T39	20		T167	20
auto[0]	values[6]	values[4]	534	1			T98	2		T111	20		T181	20
auto[0]	values[6]	values[5]	357	1			T38	50		T214	23		T134	20
auto[0]	values[6]	values[6]	253	1			T167	24		T215	12		T216	20
auto[0]	values[6]	values[7]	416	1			T39	24		T167	19		T217	10
auto[0]	values[7]	values[0]	395	1			T11	46		T111	20		T71	18
auto[0]	values[7]	values[1]	320	1			T99	8		T80	41		T218	2
auto[0]	values[7]	values[2]	435	1			T12	22		T219	10		T80	34
auto[0]	values[7]	values[3]	327	1			T12	20		T49	25		T167	75
auto[0]	values[7]	values[4]	346	1			T12	43		T80	42		T86	14
auto[0]	values[7]	values[5]	504	1			T33	88		T110	6		T40	38
auto[0]	values[7]	values[6]	328	1			T11	20		T49	20		T38	30
auto[0]	values[7]	values[7]	596	1			T12	20		T40	117		T220	24
auto[1]	values[0]	values[0]	11	1			T24	1		T221	4		T199	2
auto[1]	values[0]	values[1]	6	1			T33	3		T40	1		T51	1
auto[1]	values[0]	values[2]	3	1			T178	2		T222	1		-	-
auto[1]	values[0]	values[3]	9	1			T11	1		T223	1		T134	1
auto[1]	values[0]	values[4]	7	1			T33	1		T181	3		T165	2
auto[1]	values[0]	values[5]	5	1			T124	1		T224	2		T225	1
auto[1]	values[0]	values[6]	8	1			T40	2		T124	1		T183	1
auto[1]	values[0]	values[7]	5	1			T226	4		T227	1		-	-
auto[1]	values[1]	values[0]	3	1			T228	2		T229	1		-	-
auto[1]	values[1]	values[1]	4	1			T38	1		T230	1		T231	1
auto[1]	values[1]	values[2]	4	1			T32	2		T198	1		T232	1
auto[1]	values[1]	values[3]	3	1			T11	1		T134	2		-	-
auto[1]	values[1]	values[4]	4	1			T24	4		-	-		-	-
auto[1]	values[1]	values[5]	9	1			T12	1		T214	1		T80	1
auto[1]	values[1]	values[6]	4	1			T233	1		T234	3		-	-
auto[1]	values[1]	values[7]	5	1			T225	1		T229	1		T235	1
auto[1]	values[2]	values[0]	1	1			T40	1		-	-		-	-
auto[1]	values[2]	values[1]	6	1			T12	1		T230	3		T233	1
auto[1]	values[2]	values[2]	6	1			T236	2		T137	1		T237	3
auto[1]	values[2]	values[3]	11	1			T35	1		T238	1		T178	1
auto[1]	values[2]	values[4]	3	1			T80	1		T239	2		-	-
auto[1]	values[2]	values[5]	8	1			T195	2		T240	1		T241	3
auto[1]	values[2]	values[6]	5	1			T124	1		T230	1		T51	2
auto[1]	values[2]	values[7]	14	1			T242	2		T243	1		T238	1
auto[1]	values[3]	values[0]	3	1			T12	2		T244	1		-	-
auto[1]	values[3]	values[1]	5	1			T39	3		T198	1		T238	1
auto[1]	values[3]	values[2]	5	1			T11	3		T186	1		T245	1
auto[1]	values[3]	values[3]	18	1			T12	3		T165	1		T246	1
auto[1]	values[3]	values[4]	3	1			T178	1		T247	2		-	-
auto[1]	values[3]	values[5]	1	1			T248	1		-	-		-	-
auto[1]	values[3]	values[6]	6	1			T124	2		T165	2		T249	2
auto[1]	values[3]	values[7]	3	1			T235	3		-	-		-	-
auto[1]	values[4]	values[0]	12	1			T39	3		T80	3		T250	3
auto[1]	values[4]	values[1]	9	1			T12	1		T166	2		T42	2
auto[1]	values[4]	values[2]	14	1			T201	1		T80	2		T70	1
auto[1]	values[4]	values[3]	5	1			T12	1		T165	1		T236	1
auto[1]	values[4]	values[5]	6	1			T11	1		T39	1		T246	1
auto[1]	values[4]	values[6]	14	1			T25	3		T165	1		T251	6
auto[1]	values[4]	values[7]	3	1			T33	2		T252	1		-	-
auto[1]	values[5]	values[0]	19	1			T49	1		T40	4		T165	1
auto[1]	values[5]	values[1]	6	1			T12	1		T244	2		T227	3
auto[1]	values[5]	values[2]	6	1			T54	1		T253	2		T254	1
auto[1]	values[5]	values[3]	6	1			T80	1		T242	2		T238	1
auto[1]	values[5]	values[4]	4	1			T39	1		T255	3		-	-
auto[1]	values[5]	values[5]	6	1			T33	1		T39	2		T166	1
auto[1]	values[5]	values[6]	16	1			T40	1		T238	2		T178	2
auto[1]	values[5]	values[7]	4	1			T166	2		T256	2		-	-
auto[1]	values[6]	values[0]	8	1			T41	2		T186	1		T54	3
auto[1]	values[6]	values[1]	24	1			T12	1		T80	1		T198	3
auto[1]	values[6]	values[2]	13	1			T213	1		T178	1		T231	1
auto[1]	values[6]	values[3]	4	1			T233	1		T255	1		T257	2
auto[1]	values[6]	values[4]	8	1			T185	1		T54	1		T241	2
auto[1]	values[6]	values[5]	4	1			T38	1		T258	1		T51	2
auto[1]	values[6]	values[6]	2	1			T215	2		-	-		-	-
auto[1]	values[6]	values[7]	7	1			T167	1		T259	2		T260	1
auto[1]	values[7]	values[0]	13	1			T71	2		T236	1		T225	4
auto[1]	values[7]	values[1]	4	1			T80	1		T261	2		T255	1
auto[1]	values[7]	values[2]	4	1			T80	1		T198	2		T260	1
auto[1]	values[7]	values[3]	3	1			T49	2		T167	1		-	-
auto[1]	values[7]	values[4]	9	1			T12	2		T231	1		T262	3
auto[1]	values[7]	values[5]	13	1			T40	2		T243	1		T263	3
auto[1]	values[7]	values[6]	10	1			T38	2		T165	1		T70	2
auto[1]	values[7]	values[7]	11	1			T40	1		T236	2		T264	2