Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1928

1

T4

17

T5

7

T8

5

auto[1]

1835

1

T4

11

T5

12

T8

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2046

1

T11

35

T12

10

T30

2

auto[1]

1717

1

T4

28

T5

19

T8

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3026

1

T4

28

T5

19

T8

8

auto[1]

737

1

T11

10

T12

2

T34

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	716	1			T4	6		T5	2		T11	9
valid[1]	794	1			T4	7		T5	4		T8	2
valid[2]	774	1			T4	3		T5	4		T8	4
valid[3]	762	1			T4	7		T5	5		T8	1
valid[4]	717	1			T4	5		T5	4		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	133	1			T11	5		T12	1		T48	2
auto[0]	auto[0]	valid[0]	auto[1]	155	1			T4	5		T5	1		T16	2
auto[0]	auto[0]	valid[1]	auto[0]	146	1			T12	1		T30	1		T79	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T4	3		T5	1		T8	2
auto[0]	auto[0]	valid[2]	auto[0]	160	1			T11	3		T12	1		T48	1
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T4	2		T5	1		T8	2
auto[0]	auto[0]	valid[3]	auto[0]	129	1			T11	2		T34	2		T48	1
auto[0]	auto[0]	valid[3]	auto[1]	194	1			T4	4		T5	2		T11	1
auto[0]	auto[0]	valid[4]	auto[0]	128	1			T11	1		T34	2		T111	1
auto[0]	auto[0]	valid[4]	auto[1]	169	1			T4	3		T5	2		T8	1
auto[0]	auto[1]	valid[0]	auto[0]	109	1			T11	3		T30	1		T34	1
auto[0]	auto[1]	valid[0]	auto[1]	169	1			T4	1		T5	1		T18	1
auto[0]	auto[1]	valid[1]	auto[0]	148	1			T11	1		T12	1		T34	1
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T4	4		T5	3		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T11	1		T12	2		T34	1
auto[0]	auto[1]	valid[2]	auto[1]	175	1			T4	1		T5	3		T8	2
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T11	6		T48	1		T49	2
auto[0]	auto[1]	valid[3]	auto[1]	169	1			T4	3		T5	3		T8	1
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T11	3		T12	2		T49	2
auto[0]	auto[1]	valid[4]	auto[1]	176	1			T4	2		T5	2		T16	1
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T11	1		T49	1		T323	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T11	2		T12	1		T111	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T49	1		T39	1		T79	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T11	1		T34	1		T48	2
auto[1]	auto[0]	valid[4]	auto[0]	55	1			T11	1		T48	1		T49	1
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T48	2		T49	2		T39	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T12	1		T34	2		T48	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T11	3		T39	1		T174	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T11	2		T48	1		T49	2
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T48	1		T79	2		T40	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal