Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52071

1

T11

747

T12

230

T30

46

auto[1]

17850

1

T4

338

T5

209

T8

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50937

1

T4

338

T5

209

T8

8

auto[1]

18984

1

T11

245

T12

78

T30

15

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35663	1			T4	180		T5	102		T8	8
others[1]	6018	1			T4	34		T5	21		T11	57
others[2]	5919	1			T4	29		T5	22		T11	75
others[3]	6790	1			T4	29		T5	21		T11	86
interest[1]	3815	1			T4	12		T5	10		T11	41
interest[4]	23327	1			T4	123		T5	58		T8	8
interest[64]	11716	1			T4	54		T5	33		T11	135

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16719	1			T11	245		T12	77		T30	18
auto[0]	auto[0]	others[1]	2857	1			T11	41		T12	11		T30	3
auto[0]	auto[0]	others[2]	2887	1			T11	50		T12	10		T30	3
auto[0]	auto[0]	others[3]	3263	1			T11	54		T12	17		T30	2
auto[0]	auto[0]	interest[1]	1799	1			T11	26		T12	11		T30	2
auto[0]	auto[0]	interest[4]	10923	1			T11	157		T12	53		T30	13
auto[0]	auto[0]	interest[64]	5562	1			T11	86		T12	26		T30	3
auto[0]	auto[1]	others[0]	9235	1			T4	180		T5	102		T8	8
auto[0]	auto[1]	others[1]	1546	1			T4	34		T5	21		T11	1
auto[0]	auto[1]	others[2]	1445	1			T4	29		T5	22		T11	1
auto[0]	auto[1]	others[3]	1668	1			T4	29		T5	21		T12	2
auto[0]	auto[1]	interest[1]	950	1			T4	12		T5	10		T11	2
auto[0]	auto[1]	interest[4]	6160	1			T4	123		T5	58		T8	8
auto[0]	auto[1]	interest[64]	3006	1			T4	54		T5	33		T11	7
auto[1]	auto[0]	others[0]	9709	1			T11	119		T12	41		T30	9
auto[1]	auto[0]	others[1]	1615	1			T11	15		T12	3		T30	1
auto[1]	auto[0]	others[2]	1587	1			T11	24		T12	6		T30	1
auto[1]	auto[0]	others[3]	1859	1			T11	32		T12	9		T30	2
auto[1]	auto[0]	interest[1]	1066	1			T11	13		T12	5		T34	3
auto[1]	auto[0]	interest[4]	6244	1			T11	80		T12	25		T30	8
auto[1]	auto[0]	interest[64]	3148	1			T11	42		T12	14		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal