Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	863	1			T12	7		T34	7		T39	10
all_values[1]	863	1			T12	7		T34	7		T39	10
all_values[2]	863	1			T12	7		T34	7		T39	10
all_values[3]	863	1			T12	7		T34	7		T39	10
all_values[4]	863	1			T12	7		T34	7		T39	10
all_values[5]	863	1			T12	7		T34	7		T39	10
all_values[6]	863	1			T12	7		T34	7		T39	10
all_values[7]	863	1			T12	7		T34	7		T39	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3593

1

T12

30

T34

34

T39

43

auto[1]

3311

1

T12

26

T34

22

T39

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2668

1

T12

16

T34

31

T39

20

auto[1]

4236

1

T12

40

T34

25

T39

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3858

1

T12

29

T34

36

T39

35

auto[1]

3046

1

T12

27

T34

20

T39

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	170	1			T12	3		T34	2		T63	3
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T39	1		T63	1		T126	2
all_values[0]	auto[0]	auto[1]	auto[0]	147	1			T12	1		T34	3		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	96	1			T34	1		T39	1		T63	2
all_values[0]	auto[1]	auto[0]	auto[1]	195	1			T12	3		T39	4		T63	4
all_values[0]	auto[1]	auto[1]	auto[1]	183	1			T34	1		T39	3		T63	3
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T12	1		T34	1		T39	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T12	2		T34	1		T63	2
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T34	1		T63	2		T126	1
all_values[1]	auto[0]	auto[1]	auto[1]	86	1			T34	1		T39	4		T63	2
all_values[1]	auto[1]	auto[0]	auto[1]	206	1			T12	2		T34	1		T39	4
all_values[1]	auto[1]	auto[1]	auto[1]	174	1			T12	2		T34	2		T39	1
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T12	1		T34	3		T39	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T12	1		T39	2		T63	3
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T12	1		T63	2		T126	2
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T12	1		T63	1		T163	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T12	2		T34	2		T39	5
all_values[2]	auto[1]	auto[1]	auto[1]	192	1			T12	1		T34	2		T39	1
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T34	3		T39	6		T126	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T12	1		T63	2		T164	1
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T12	1		T34	1		T63	2
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T12	1		T34	1		T63	1
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T12	2		T34	1		T39	2
all_values[3]	auto[1]	auto[1]	auto[1]	177	1			T12	2		T34	1		T39	2
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T12	1		T34	3		T126	1
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T12	1		T34	1		T164	2
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T34	1		T39	5		T63	2
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T12	2		T63	3		T126	1
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T12	1		T34	1		T39	2
all_values[4]	auto[1]	auto[1]	auto[1]	187	1			T12	2		T34	1		T39	3
all_values[5]	auto[0]	auto[0]	auto[0]	237	1			T12	2		T34	2		T63	3
all_values[5]	auto[0]	auto[1]	auto[0]	247	1			T12	3		T34	2		T39	4
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T34	2		T39	4		T63	2
all_values[5]	auto[1]	auto[1]	auto[1]	179	1			T12	2		T34	1		T39	2
all_values[6]	auto[0]	auto[0]	auto[0]	168	1			T34	4		T63	4		T126	3
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T12	1		T39	3		T63	2
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T34	1		T63	2		T126	1
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T12	2		T39	2		T63	1
all_values[6]	auto[1]	auto[0]	auto[1]	220	1			T12	3		T34	2		T39	3
all_values[6]	auto[1]	auto[1]	auto[1]	164	1			T12	1		T39	2		T63	2
all_values[7]	auto[0]	auto[0]	auto[0]	193	1			T12	2		T34	2		T39	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T63	2		T126	2		T163	1
all_values[7]	auto[0]	auto[1]	auto[0]	138	1			T34	2		T63	5		T126	1
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T12	1		T39	2		T126	2
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T12	1		T34	3		T39	3
all_values[7]	auto[1]	auto[1]	auto[1]	183	1			T12	3		T39	4		T63	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal